Abstract: A process of forming a multi-layer electronic composite structure. The process includes providing at least one core including at least one plane of at least one electrically conducting material with a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material. The at least one core includes a plurality of placed through holes formed therethrough. At least one pad is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device and also prevents solder from entering the at least one plated through hole.

Abstract: Disclosed is a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a novel fixture for holding the substrate and a novel mask for 1-step photolithographic exposure. The result of the invention is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.

Abstract: A process of forming a multi-layer electronic composite structure. The process includes providing at least one core including at least one plane of at least one electrically conducting material with a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material. The at least one core includes a plurality of plated through holes formed therethrough. At least one pad is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device and also prevents solder from entering the at least one plated through hole.

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.

Abstract: A process of forming a multi-layer electronic composite structure. At least one core including at least one functional plane of at least one electrically conducting material having a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material is provided. The at least one core includes a plurality of plated through holes formed therethrough. A pad of an electrically-conducting material is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device. The pad also prevents solder from entering the at least one plated through hole. Additionally, the pad provides an electrical connection between the electronic device and the at least one core.

Abstract: A cap for attaching a chip or other device to a multi-layer electronic structure. The cap includes a plurality of pads of an electrically-conducting material attached over plated through holes of the multi-layer electronic structure. Each of the pads includes a flat upper surface for attaching the chip or other device to the multi-layer structure, provides an electrical connection between the chip or other device and the multi-layer structure, and seals the through holes to prevent solder from entering the plated through hole. The pads are physically isolated from each other.