Abstract: A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

Abstract: Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

Abstract: Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

Abstract: A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

Abstract: A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.

Abstract: A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.

Abstract: A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.

Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

Abstract: Embodiments of the invention are directed to using a trained machine learning model to generate predicted circuit data for a circuit design, and computing an objective function using the predicted circuit data. Optimization of the objective function is performed to generate an optimal solution, and the optimal solution is mapped to the circuit design.

Abstract: A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.

Abstract: A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

Abstract: Using a burn-in operational amplifier (opamp) for a phased locked loop (PLL) regulator including activating a voltage stress mode for an integrated circuit comprising a PLL regulator for a PLL, wherein the PLL regulator comprises thin-oxide transistors, and wherein activating the voltage stress mode for the integrated circuit comprises applying an elevated voltage to an input of the PLL regulator; and enabling, during the voltage stress mode, a burn-in opamp coupled to the input of the PLL regulator, wherein enabling the burn-in opamp bias the input of the PLL regulator to a voltage lower than the elevated voltage.

Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

Abstract: Using a burn-in operational amplifier (opamp) for a phased locked loop (PLL) regulator including activating a voltage stress mode for an integrated circuit comprising a PLL regulator for a PLL, wherein the PLL regulator comprises thin-oxide transistors, and wherein activating the voltage stress mode for the integrated circuit comprises applying an elevated voltage to an input of the PLL regulator; and enabling, during the voltage stress mode, a burn-in opamp coupled to the input of the PLL regulator, wherein enabling the burn-in opamp bias the input of the PLL regulator to a voltage lower than the elevated voltage.

Abstract: Medical devices include stimulation and/or sensing circuitry that is interconnected to electrical components by a flexible circuit body having exposed portions of circuit traces that are attached to electrical contacts of the electrical components. Each circuit trace may span a separate window formed in an insulative body of the flexible circuit body, or a plurality of circuit traces may span a single window or may be freely extending from the insulative body. The exposed portion of the circuit trace may be plated with a conductive metal and then attached to the electrical contact of the electrical component. The flexible circuit body may be an extension from a flexible electrical circuit board containing the circuit. The circuit may be present on a circuit board that includes electrical contacts and where the flexible circuit body has exposed portions of circuit traces attached to the electrical contacts of the circuit board.

Abstract: Medical devices include stimulation and/or sensing circuitry that is interconnected to electrical components by a flexible circuit body having exposed portions of circuit traces that are attached to electrical contacts of the electrical components. Each circuit trace may span a separate window formed in an insulative body of the flexible circuit body, or a plurality of circuit traces may span a single window or may be freely extending from the insulative body. The exposed portion of the circuit trace may be plated with a conductive metal and then attached to the electrical contact of the electrical component. The flexible circuit body may be an extension from a flexible electrical circuit board containing the circuit. The circuit may be present on a circuit board that includes electrical contacts and where the flexible circuit body has exposed portions of circuit traces attached to the electrical contacts of the circuit board.

Abstract: Medical devices include stimulation and/or sensing circuitry that is interconnected to electrical components by a flexible circuit body having exposed portions of circuit traces that are attached to electrical contacts of the electrical components. Each circuit trace may span a separate window formed in an insulative body of the flexible circuit body, or a plurality of circuit traces may span a single window or may be freely extending from the insulative body. The exposed portion of the circuit trace may be plated with a conductive metal and then attached to the electrical contact of the electrical component. The flexible circuit body may be an extension from a flexible electrical circuit board containing the circuit. The circuit may be present on a circuit board that includes electrical contacts and where the flexible circuit body has exposed portions of circuit traces attached to the electrical contacts of the circuit board.

Abstract: A connector assembly for an implantable medical device includes a plurality of feedthroughs mounted in a conductive array plate, each feedthrough in the plurality of feedthroughs including a feedthrough pin electrically isolated from the conductive array plate by an insulator and an electronic module assembly including a plurality of conductive strips set in a non-conductive block. The plurality of conductive strips is in physical and electrical contact with the feedthrough pins at an angle of less than 135 degrees. The connector assembly further includes at least one circuit, the circuit including a plurality of conductors corresponding to the plurality of feedthroughs. The plurality of conductors of the circuit is in physical and electrical contact with a corresponding one of the conductive strips of the plurality of conductive strips of the electronic module assembly at an angle of less than 135 degrees.