Abstract: The method of the invention enables a computer to examine a software application, which includes operands and operators, and to identify operand fields which include a year value. A scan knowledge base includes scan rules that enable characteristics of operands to recognized, identified and initially classified. An operand association table is provided for each operator and indicates, based upon inter-relationships of operands associated with the operator, whether an associated operand that has been initially classified as a year field or a probable year field, should be assigned a revised classification and what that revised classification should be. The method reviews the application, using the scan knowledge base, to identify each operand which can be initially classified as a year field or a probable year field and lists each such operand in an operand table.

Abstract: A method determines if a revised fragment of a program provides an identical answer as does an original fragment of the program, wherein a fragment is one operator and one or more operands that are subject to processing by the operator. The method comprises the steps of: executing both an original fragment of the program and one or more revised fragment(s) which correspond to the original fragment, using first equvalent variables and determining if both fragments produce equivalent results; executing both the revised fragment(s) and the original fragment of the program using additional variables to determine if both fragments produce equivalent results under all test conditions; if the results are not equivalent, making a notation of that fact for later examination; and if the fragments are equivalent, repeating the aforementioned test steps until all revised code fragments have been tested.

Abstract: The method of the invention enables a computer to examine a software application, which includes operands and operators, and to identify operand fields which include a year value. An operand association table is provided for each operator and indicates, based upon inter-relationships of operands associated with the operator, whether an associated operand that has been classified as a year field or a probable year field, should be assigned a revised classification and what that revised classification should be. The method reviews the application to identify each operand which can be initially classified as a year field or a probable year field and lists each such operand in an operand table. The method also reviews the application to identify every operator listed therein and lists every operator and any associated operands in an operator table.

Abstract: A binary date format, hereafter referred to as "packed binary", is used and comprises a 2-byte data field. The first two bits of the data field are utilized as identifiers to enable the packed binary format to be identified. The remaining bits are employed as a binary value year indication. A date conversion procedure employs the packed binary format and is called when a program reaches a date field that is to be processed. The date conversion procedure initially examines the date field to determine whether its format is zone decimal, packed decimal or packed binary. If the date field data format is either zone decimal or packed decimal, the date values are converted to packed decimal and the required arithmetic procedure is performed, using the packed binary format date value. Once the calculation is complete, the procedure determines whether a "year 2000" switch is set--indicating that all results are to be returned to the program in packed binary format.

Abstract: A software-controlled data processing system employs control blocks, each control block including a data structure that defines at least one control parameter for a data processing action. Plural control blocks are assigned to the data processing action to enable its performance, and each of the plural control blocks has a tag value which, for any set of chained control blocks assigned to the data processing action, exhibit an identical value. The data processing method comprises the steps of: executing the data processing action by accessing each of the plural assigned control blocks in a sequence; comparing tag values contained in sequentially accessed control blocks to determine if the tag values are identical and, if yes, continuing execution of the data processing action and, if no, reporting an anomaly. Such a procedure enables the data processing system to assure that the received, chained control blocks are all assigned to a common data processing action.

Abstract: A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting.

Abstract: Updating of control code is accomplished in multiple nodes of a computing system while the computing system remains in operation. Each node includes a processor, memory, a first version of a control code unit and an engineering change level indication for the control code unit. The method comprises the steps of: installing a revised version of the control code unit with converter code modules in a first node, the converter code modules enabling and performing first and second interface functions during communications between the first node and other nodes in the system. The first node is then operated to perform a function which requires communication with other nodes, the converter code module in the first node initially determining an engineering change level value stored in another node and, if the engineering change level values in the nodes match, communicating with the other node through the first interface function.

Abstract: A computer-implemented method for translating from one DASD address to another DASD address initially stores a plurality of translation tables, one translation table for each first DASD coupled to a first processor. Each translation table includes at least a first data value for each cylinder in a first DASD which indicates whether or not the cylinder contains a start-of-extent address. If yes, the translation table has a corresponding translation entry which includes a first portion and a second portion. The first portion includes at least the start-of-extent address in the cylinder and a length of the extent of addresses associated with the start-of-extent address. The second portion includes a start-of-extent address for an address span in a second DASD that corresponds to the first portion.

Abstract: A multi-nodal computing system is connected by a communication network. A first node of the multi-nodal system includes apparatus for transmitting an information transfer request to a second node, the request including identification data that the second node can use to access the selected information. The second node includes memory for storing the requested information and a message output control structure. A processor is responsive to received identification data from the first node to access selected information that is defined by the data. The processor is further responsive to the information transfer request to insert the identification data received from the first node directly into a message output control structure. The processor then initiates an output operation by employing the identification data in the message output control data structure to access the identified information and to communicate the information to the first node.

Abstract: A multi-node data processing system implements a method that assures that plural messages are enabled "fair" access to a data stream. Each node includes apparatus for controlling message transmissions and/or receptions from another node over a communication network. The method comprises the steps of: transmitting a routing message from a first destination node to a source node, the routing message signalling a readiness of the destination node to receive a data message; transmitting a first data message to the first destination node from the source node in response to the ready message; transmitting a conditional disconnect message from the first destination node to the source node upon receipt of a predetermined amount (i.e. a "slice") of the first data message.

Abstract: A parallel computing system includes multiple nodes, each node including a processor with software control. The parallel computing system includes a distributed lock mechanism that controls access to system resources, the lock mechanism distributed among the multiple nodes, with each node including hardware-based lock processing apparatus. Such apparatus comprises a communication interface for receiving and transmitting control and data messages and a table arrangement for storing plural lock words. A state machine is present in each node and is connected to the table arrangement and to the communications interface and is responsive to a received lock request to perform hardware-controlled lock processing functions.

Abstract: A data processing system includes a software interrupt handler which controls performance of interrupt actions. The system further includes plural subsystems, each subsystem manifesting an interrupt request upon occurrence of an associated event. Hardware is provided which responds to an interrupt request by issuing an order to construct an interrupt status block (ISB) control data structure with a determined priority ranking. A controller is responsive to the issued order and constructs the ISB data structure. The ISB at least includes a pointer value indicating a next ISB having a same priority ranking, interrupt data identifying an interrupt procedure to be used by the software interrupt handler and information indicating a source of the interrupt request. The controller arranges the ISB in a queue of ISB's having a same determined priority and signals the software interrupt handler to commence performance of an interrupt action only if the order issued by the hardware requires an immediate interrupt.

Abstract: In a multinode communication or multiprocessor network, messages are communicated from one node to another using an adaptive and dynamic routing scheme. The routing scheme includes two-level multi-path routing tables at each node to ensure efficient delivery of the messages. An entry in the level-1 table identifies a group of nodes and entry in the level-2 table identifies the address for each node within that group. The routing scheme also includes a deflection counter in each message header to avoid endless rerouting of messages and an exponential backoff and retry policy to avoid deadlocks.

Abstract: The data contents of up to two concurrently failed or erased DASDs can be reconstituted where the data is distributed across M DASDs as an (M-1)*M block array and where (1) the (M-1)st DASD contains the simple parity taken over each of the array diagonals in diagonal major order in the same mode (odd/even) as that exhibited by the major diagonal of the array and (2) where the M-th DASD contains the simple even parity over each of the rows in row major order. Relatedly, short write updates require fewer operations for data blocks located off the major data array diagonal.

Abstract: A computing system includes plural nodes that are connected by a communications network. Each node comprises a communications interface that enables an exchange of messages with other nodes. A ready queue is maintained in a node and includes plural message entries, each message entry indicating an output message control data structure. The node further includes memory for storing plural output message control data structures, each including one or more chained further monrtol data structures that define data comprising a message or a portion of a message that is to be dispatched. Control data structures that are chained from an output messsage control data structure exhibit a sequence dependincy. A processor is controlled by the ready queue and enables dispatch of portions of the message designated by an output message control data structure and associated further control structures.

Abstract: A data storage system and method for operating a disk controller, and also a disk controller operated in accordance with the method are disclosed. The method includes the steps of allocating a first amount of disk space for a compressed data unit as a first predetermined percentage of an uncompressed size of the data unit; and then increasing the allocation by a second predetermined percentage that is less than the first predetermined percentage to obtain a total amount of allocated disk space. The first predetermined percentage is a function of an expected compression ratio for the data unit, and the second predetermined percentage is a function of an expected change in the size of the compressed data unit as a result of an update operation performed on the data unit.

Abstract: A method and apparatus for ensuring the communication of a minimal length data stream in a system including a host and a storage management device is provided. The method and apparatus includes first and second buffers for simultaneously receiving compressed data and the original data from the host. The system compares the length of the data in the first and second buffers. If the data has expanded, indicating that compressed data is longer than the original data, the original data is provided to the storage media. If the data has not expanded, indicating that the original data is longer than the compressed data, then the compressed data is provided to the storage media.

Abstract: In a log structured array (LSA) storage subsystem, a method for recovering from a storage device failure which incorporates the LSA write and garbage collection procedures, thereby simplifying the recovery process and eliminating the need for dedicated or distributed sparing schemes. Data is distributed across the array in N+P parity groups. Upon a device failure, each lost data block is reconstructed from the remaining blocks of its parity group. The reconstructed block is then placed in the subsystem write buffer to be processed with incoming write data, and new parity is generated for the remaining N-1 data blocks of the group. A lost parity block is replaced by first moving one of the data blocks of its parity group to the write buffer, and then generating new parity for the remaining N-1 data blocks. Also disclosed is a storage subsystem implementing the preceding recovery method.

Abstract: A memory controller performs parity encoding on a plurality of data strings moving between a memory connected via a read path to a data bus connected to a corresponding plurality of storage devices. A write buffer has one input for receiving data for storage in the memory and another input for receiving data from the memory for parity calculation. Two outputs of the write buffer are connected to a parity generator. Circuitry responsive to control signals from the data bus conditions the parity generator to logically and recursively combine the two outputs of the write buffer for supplying an updated parity calculation to the memory via a write path. To provide error detection and correction an ECC generator is interposed between the write path and the parity generator, and an ECC check/correction unit is interposed between the read path and control-signal-responsive circuity. The parity encoding is performed using a code that is associative and commutative.

Abstract: A method and apparatus for avoiding line-accessed cache misses during a replacement/selection (tournament) sorting process. Prior to the sorting phase, the method includes the steps of sizing and writing maximal sets of sub-tree nodes of a nested ordering of keys, suitable for staging as cache lines. During the sort phase, the method includes the steps of prefetching into cache from CPU main memory one or more cache lines formed from a sub-tree of ancestor nodes immediate to the node in cache just selected for replacement. The combination of the clustering of ancestor nodes within individual cache lines and the prefetching of cache lines upon replacement node selection permits execution of the full tournament sort procedure without the normally-expected cache miss rate. For selection trees larger than those that can fit entirely into cache, the method avoids the second merge phase overhead that formerly doubled the sorting time necessary for larger cache sizes.