Abstract: Circuitry for processing a sense signal obtained from an electrochemical cell having a first electrode and a second electrode, the circuitry comprising: drive circuitry configured to apply a first voltage at a first electrode; measurement circuitry configured to measure the sense current at the second electrode and output a sense signal based on the measured sense current; control circuitry configured to: generate an output signal based on the sense signal; and adapt the first voltage based on the output signal.

Abstract: Circuitry for processing an analyte signal obtained from an electrochemical cell, the circuitry comprising: a converter, comprising: a first converter input configured to receive the analyte signal; a second converter input; and a converter output configured to output a converted analyte signal, the converter configured to generate the converted analyte signal in dependence on the analyte signal; a loop filter configured to filter a signal derived from the converted analyte signal to obtain a filtered analyte signal at a filter output; and a feedback path between the filter output and the second converter input.

Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element. There is further described programmable resistance cells using charge-trapping-transistors (CTTs) and analog signal processing circuits using CTTs to provide tuneability.

Abstract: Circuitry for processing an analyte signal obtained from an electrochemical cell, the circuitry comprising: a first input node for receiving the analyte signal; measurement circuitry having a first signal path coupled to the first input node, the measurement circuitry configured to output an output signal based on the analyte signal, the measurement circuitry comprising a first circuit element having a first impedance, the first circuit element coupled to the first signal path; and control circuitry configured to reset one or more first voltages in the first signal path of the measurement circuitry to a respective first reference value.

Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

Abstract: Coulomb counter circuitry operable in a first mode of operation and a second mode of operation, the coulomb counter circuitry comprising: first analog to digital converter (ADC) circuitry configured to generate a first ADC output signal indicative of a current through a load coupled to the coulomb counter circuitry; second analog to digital converter (ADC) circuitry; offset correction circuitry; and accumulator circuitry configured to generate a signal indicative of a cumulative amount of charge transferred to the load, wherein in the second mode of operation, the coulomb counter circuitry is operable to enable the second ADC circuitry and to generate an offset correction factor based at least in part on a second ADC output signal output by the second ADC circuitry, and wherein in subsequent operation of the coulomb counter circuitry in the first mode of operation, the offset correction circuitry applies the offset correction factor to the first ADC output signal.

Abstract: A circuit may include a two-stage feedforward compensated operational transconductance integrated amplifier, and the two-stage feedforward compensated operational transconductance integrated amplifier may include an input terminal, an output terminal, a signal path between the input terminal and the output terminal, the signal path comprising a first signal path gain stage and a second signal path gain stage, and ripple rejection circuitry coupled between the input terminal and an intermediate node of the signal path located between the first signal path gain stage and the second signal path gain stage.