Patents by Inventor James T. Doyle
James T. Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929673Abstract: An assembly includes a three-level voltage converter and a second voltage converter. The three-level voltage converter is electrically coupled to a battery to convert a battery supply voltage to an intermediate voltage. The second voltage converter is electrically coupled to the three-level voltage converter to convert the intermediate voltage to a processor-supply voltage to operate a processor. At least the second voltage converter and the processor are mounted on a processor-package substrate. The three-level voltage converter can be mounted on the processor-package substrate or on a circuit board on which the processor-package substrate is mounted.Type: GrantFiled: October 29, 2021Date of Patent: March 12, 2024Assignee: Ferric Inc.Inventors: Francesco Carobolante, James T. Doyle, Noah Andrew Sturcken
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Patent number: 11876455Abstract: The present document relates to power converters. A power converter may be configured to convert an input voltage at an input of the power converter into an output voltage at an output of the power converter. The power converter may comprise a first switching circuit with a first inductor, a first high-side switching element, and a first low-side switching element. The power converter may comprise a second switching circuit with a second inductor, a second high-side switching element, and a second low-side switching element. The power converter may comprise a capacitive element having a first terminal coupled to the first high-side switching element and to the second high-side switching element and having a second terminal coupled to the first low-side switching element at a first node. The power converter may comprise a third switching element coupled between the first node and the output of the power converter.Type: GrantFiled: January 14, 2022Date of Patent: January 16, 2024Assignee: Dialog Semiconductor (UK) LimitedInventors: Milan Dragojevic, James T. Doyle, Ambreesh Bhattad
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Publication number: 20230139978Abstract: An assembly includes a three-level voltage converter and a second voltage converter. The three-level voltage converter is electrically coupled to a battery to convert a battery supply voltage to an intermediate voltage. The second voltage converter is electrically coupled to the three-level voltage converter to convert the intermediate voltage to a processor-supply voltage to operate a processor. At least the second voltage converter and the processor are mounted on a processor-package substrate. The three-level voltage converter can be mounted on the processor-package substrate or on a circuit board on which the processor-package substrate is mounted.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Francesco Carobolante, James T. Doyle, Noah Andrew Sturcken
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Patent number: 11469664Abstract: The present document describes a power converter configured to provide energy at an output based on energy provided at an input. The power converter comprises a first switch, wherein a first node is coupled to the input and wherein a second node is coupled to an intermediate point, a second switch, wherein a first node is coupled to the intermediate point and wherein a second node is coupled to an inductor point, a capacitor, wherein a first node of the capacitor is coupled to the intermediate point, a first diode element, wherein a first node is coupled to a second node of the capacitor and wherein a second node is coupled to the inductor point, a second diode element, wherein a first node is coupled to a reference port, and wherein a second node is coupled to the second node of the capacitor; and an inductor, wherein a first node is coupled to the inductor point and wherein a second node is coupled to the output.Type: GrantFiled: February 26, 2021Date of Patent: October 11, 2022Assignee: Dialog Semiconductor (UK) LimitedInventors: Ambreesh Bhattad, Horst Knoedgen, James T. Doyle, Milan Dragojevic
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Publication number: 20220231607Abstract: The present document relates to power converters. A power converter may be configured to convert an input voltage at an input of the power converter into an output voltage at an output of the power converter. The power converter may comprise a first switching circuit with a first inductor, a first high-side switching element, and a first low-side switching element. The power converter may comprise a second switching circuit with a second inductor, a second high-side switching element, and a second low-side switching element. The power converter may comprise a capacitive element having a first terminal coupled to the first high-side switching element and to the second high-side switching element and having a second terminal coupled to the first low-side switching element at a first node. The power converter may comprise a third switching element coupled between the first node and the output of the power converter.Type: ApplicationFiled: January 14, 2022Publication date: July 21, 2022Inventors: Milan Dragojevic, James T. Doyle, Ambreesh Bhattad
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Patent number: 11223277Abstract: The present document describes a power converter configured to provide energy at an output based on energy provided at an input. The power converter comprises a first switch, wherein a first node is coupled to the input and wherein a second node is coupled to an intermediate point, a second switch, wherein a first node is coupled to the intermediate point and wherein a second node is coupled to an inductor point, a capacitor, wherein a first node of the capacitor is coupled to the intermediate point, a first diode element, wherein a first node is coupled to a second node of the capacitor and wherein a second node is coupled to the inductor point, a second diode element, wherein a first node is coupled to a reference port, and wherein a second node is coupled to the second node of the capacitor; and an inductor, wherein a first node is coupled to the inductor point and wherein a second node is coupled to the output.Type: GrantFiled: September 12, 2019Date of Patent: January 11, 2022Assignee: Dialog Semiconductor (UK) LimitedInventors: Ambreesh Bhattad, Horst Knoedgen, James T. Doyle, Milan Dragojevic
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Publication number: 20210184568Abstract: The present document describes a power converter configured to provide energy at an output based on energy provided at an input. The power converter comprises a first switch, wherein a first node is coupled to the input and wherein a second node is coupled to an intermediate point, a second switch, wherein a first node is coupled to the intermediate point and wherein a second node is coupled to an inductor point, a capacitor, wherein a first node of the capacitor is coupled to the intermediate point, a first diode element, wherein a first node is coupled to a second node of the capacitor and wherein a second node is coupled to the inductor point, a second diode element, wherein a first node is coupled to a reference port, and wherein a second node is coupled to the second node of the capacitor; and an inductor, wherein a first node is coupled to the inductor point and wherein a second node is coupled to the output.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Inventors: Ambreesh Bhattad, Horst Knoedgen, James T. Doyle, Milan Dragojevic
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Publication number: 20210083582Abstract: The present document describes a power converter configured to provide energy at an output based on energy provided at an input. The power converter comprises a first switch, wherein a first node is coupled to the input and wherein a second node is coupled to an intermediate point, a second switch, wherein a first node is coupled to the intermediate point and wherein a second node is coupled to an inductor point, a capacitor, wherein a first node of the capacitor is coupled to the intermediate point, a first diode element, wherein a first node is coupled to a second node of the capacitor and wherein a second node is coupled to the inductor point, a second diode element, wherein a first node is coupled to a reference port, and wherein a second node is coupled to the second node of the capacitor; and an inductor, wherein a first node is coupled to the inductor point and wherein a second node is coupled to the output.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: Ambreesh Bhattad, Horst Knoedgen, James T. Doyle, Milan Dragojevic
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Patent number: 9064116Abstract: Techniques for a data storage device to locally implement security management functionality. In an embodiment, a security management process of the data storage device is to determine whether an access to non-volatile media of the data storage device is authorized. In certain embodiments, the data storage device is to restrict access to a secure region of the non-volatile storage media, the secure region to store information used and/or generated by a security management process of the data storage device.Type: GrantFiled: November 8, 2010Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Nicholas D. Triantafillou, Paritosh Saxena, Robert W. Strong, Richard J. Heiler, Eliezer Tamir, Simoni Ben-Michael, Brad W. Stewart, Akshay R. Kadam, Men Long, James T. Doyle, Hormuzd M. Khosravi, Lokpraveen B. Mosur, Edward J. Pullin, Paul S. Schmitz, Carol L. Barrett, Paul J. Thadikaran
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Patent number: 8618788Abstract: In some embodiments, a multi-phase converter with dynamic phase adjustment is provided. In some embodiments, a controller may include circuitry to control how many phase legs are active based on output current and also which phase legs are to be enabled.Type: GrantFiled: March 30, 2007Date of Patent: December 31, 2013Inventors: Malay Trivedi, Erik A. McShane, James T. Doyle
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Patent number: 8253405Abstract: In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.Type: GrantFiled: December 31, 2008Date of Patent: August 28, 2012Inventors: Malay Trivedi, Jiang William, Brent D. Thomas, James T. Doyle, Rose Wang
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Publication number: 20120117348Abstract: Techniques for a data storage device to locally implement security management functionality. In an embodiment, a security management process of the data storage device is to determine whether an access to non-volatile media of the data storage device is authorized. In certain embodiments, the data storage device is to restrict access to a secure region of the non-volatile storage media, the secure region to store information used and/or generated by a security management process of the data storage device.Type: ApplicationFiled: November 8, 2010Publication date: May 10, 2012Inventors: Nicholas D. Triantafillou, Paritosh Saxena, Robert W. Strong, Richard J. Heiler, Eliezer Tamir, Simoni Ben-Michael, Brad W. Stewart, Akshay R. Kadam, Men Long, James T. Doyle, Hormuzd M. Khosravi, Lokpraveen B. Mosur, Edward J. Pullin, Paul S. Schmitz, Carol L. Barrett, Paul J. Thadikaran
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Patent number: 8151125Abstract: A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the adaptive voltage scaling (AVS) system. The present invention provides multi-point calibration by calibrating a Reference Calibration Code (RCC) for each operating point (clock frequency) of the adaptive voltage scaling (AVS) system.Type: GrantFiled: August 11, 2009Date of Patent: April 3, 2012Assignee: National Semiconductor CorporationInventors: Mark Hartman, James T. Doyle, Dragan Maksimovic, Pasi Salmi, Juha Pennanen, Sandeep Dhar
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Patent number: 7952160Abstract: Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.Type: GrantFiled: December 31, 2007Date of Patent: May 31, 2011Assignee: Intel CorporationInventors: Nicholas D. Triantafillou, Malay Trivedi, Erik A. McShane, James T. Doyle, Mark J. Kachmarek
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Patent number: 7852252Abstract: Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth.Type: GrantFiled: December 31, 2008Date of Patent: December 14, 2010Assignee: Intel CorporationInventors: Fuding Ge, Brent D. Thomas, Malay Trivedi, James T. Doyle
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Publication number: 20100164477Abstract: In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Malay Trivedi, Jiang William, Brent D. Thomas, James T. Doyle, Rose Wang
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Publication number: 20100164622Abstract: Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Fuding Ge, Brent D. Thomas, Malay Trivedi, James T. Doyle
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Patent number: 7729459Abstract: A system and method is disclosed for providing a robust ultra low power serial interface with a digital clock and data recovery circuit for power management systems. In one advantageous embodiment a digital clock and data recovery circuit of the invention comprises a quadruple phase clock generator circuit that generates four shifted clock signals, a decision logic circuit, a state detector circuit, and an edge detector circuit. The detected edges of data signals are used to latch the state of the four shifted clock signals. The state detector circuit selects a stable clock signal among the four shifted clock signals for use as a recovered clock signal and synchronizes the recovered clock signal at a center of the data signal. The selected recovered clock signal remains available until another data signal transition is detected.Type: GrantFiled: March 31, 2005Date of Patent: June 1, 2010Assignee: National Semiconductor CorporationInventors: Dae Woon Kang, James T. Doyle
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Patent number: 7676239Abstract: A method for operating a power controller in a wireless communication device is provided that includes generating a power controller output signal using an open loop polar modulation scheme. The power controller output signal is operable to control the power delivered to a high-band power amplifier and a low-band power amplifier. A band state is determined for the wireless communication device. The power controller output signal is provided to the high-band power amplifier when the band state is a high-band state and to the low-band power amplifier when the band state is a low-band state.Type: GrantFiled: February 24, 2005Date of Patent: March 9, 2010Assignee: National Semiconductor CorporationInventors: James T. Doyle, Dae Woon Kang
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Publication number: 20100033236Abstract: Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.Type: ApplicationFiled: December 31, 2007Publication date: February 11, 2010Inventors: Nicholas D. TRIANTAFILLOU, Malay TRIVEDI, Erik A. MCSHANE, James T. DOYLE, Mark J. KACHMAREK