Abstract: A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscillator which utilizes two capacitors. Two signals are used to drive a first, larger, capacitor, and have the same duty cycle when the capacitor voltage is proper and the voltage controlled oscillator is operating at the correct frequency. A second, smaller, capacitor is used to quickly achieve phase lock with the incoming data signal. The use of two oppositional signals to drive the capacitors allows them to more quickly be charged or discharged to the proper voltage level to obtain both frequency and phase lock with the incoming data signal. Thus, the circuit is able to quickly acquire lock during power-up, or reacquire lock under circumstances where the operating condition of the circuit changes suddenly.

Abstract: A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscillator which utilizes two capacitors. Two signals are used to drive a first, larger, capacitor, and have the same duty cycle when the capacitor voltage is proper and the voltage controlled oscillator is operating at the correct frequency. A second, smaller, capacitor is used to quickly achieve phase lock with the incoming data signal. The use of two oppositional signals to drive the capacitors allows them to more quickly be charged or discharged to the proper voltage level to obtain both frequency and phase lock with the incoming data signal. Thus, the circuit is able to quickly acquire lock during power-up, or reacquire lock under circumstances where the operating condition of the circuit changes suddenly.

Abstract: A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscillator which utilizes two capacitors. Two signals are used to drive a first, larger, capacitor, and have the same duty cycle when the capacitor voltage is proper and the voltage controlled oscillator is operating at the correct frequency. A second, smaller, capacitor is used to quickly achieve phase lock with the incoming data signal. The use of two oppositional signals to drive the capacitors allows them to more quickly be charged or discharged to the proper voltage level to obtain both frequency and phase lock with the incoming data signal. Thus, the circuit is able to quickly acquire lock during power-up, or reacquire lock under circumstances where the operating condition of the circuit changes suddenly.

Abstract: A synchronizer in a receiver for a serial data stream includes a shift register for temporarily storing the most recently received data. Taps at a plurality of locations on such shift register provide bit signals at regularly spaced locations. These bit signals are checked for the occurrence of predetermined patterns which indicate the occurrence of frame bit candidates. A candidate shift register indicates which bit positions currently remain as candidates for the frame bit position, and is shifted synchronously with the incoming data. The candidate shift register is N bits in length, and a modulo-N counter is connected to the serial output thereof. Each time a bit position shifted out of the candidate register contains a valid candidate, the modulo-N counter is reset. When the counter counts for a full cycle, the true frame bit position has been identified.

Abstract: A synchronizer in a receiver for a serial data stream includes a shift register for temporarily storing the most recently received data. Taps at a plurality of locations on such shift register provide bit signals at regularly spaced locations. A cyclic shift register is clocked each time a true frame bit is received. Combinational logic connected to the data taps determines whether a pattern indicating a possible multiframe alignment exists at the data taps. Multiframe candidates are stored in the cycle shift register until all but one are eliminated, with the remaining candidate indicating multiframe alignment.