Abstract: A device and system for purifying a fluid is provided. The system includes a tank having an interior space and a media container disposed within the interior space. A valve is provided that cooperates with an element within the interior, the valve being movable between an open and a closed position. The valve being biased to the open position when the element is not positioned within the interior space, wherein the interior space is fluidly coupled to the atmosphere in the open position. The valve further being configured to move to a closed position when the element is positioned within the interior space.

Abstract: A device and system for purifying a fluid is provided. The system includes a tank having an interior space and a media container disposed within the interior space. A valve is provided that cooperates with an element within the interior, the valve being movable between an open and a closed position. The valve being biased to the open position when the element is not positioned within the interior space, wherein the interior space is fluidly coupled to the atmosphere in the open position. The valve further being configured to move to a closed position when the element is positioned within the interior space.

Abstract: Provided are bispecific antibody compounds having the Formula I: wherein, FAB1, FAB2, and —X— are as defined herein. The provided bispecific antibody compounds can be used a modulators of target molecules, including CD3, PSMA, CD19, CXCR5, CD33, PDL1, VEGFR2, cMet, or Axl, and are useful in the treatment of one or more conditions.

Abstract: Provided are bispecific antibody compounds having the Formula I: wherein, FAB1, FAB2, and —X— are as defined herein. The provided bispecific antibody compounds can be used a modulators of target molecules, including CD3, PSMA, CD19, CXCR5, CD33, PDL1, VEGFR2, cMet, or Ax1, and are useful in the treatment of one or more conditions.

Abstract: Provided are bispecific conjugates having the general formula: pharmaceutically acceptable salts thereof, pharmaceutical compositions thereof, and their use in the treatment of cancer.

Abstract: Provided are bispecific conjugates having the general formula: pharmaceutically acceptable salts thereof, pharmaceutical compositions thereof, and their use in the treatment of cancer.

Abstract: Provided are bispecific antibody compounds having the Formula I: wherein, FAB1, FAB2, and —X— are as defined herein. The provided bispecific antibody compounds can be used a modulators of target molecules, including CD3, PSMA, CD19, CXCR5, CD33, PDL1, VEGFR2, cMet, or Ax1, and are useful in the treatment of one or more conditions.

Abstract: Provided are bispecific antibody compounds having the Formula I: wherein, FAB1, FAB2, and —X— are as defined herein. The provided bispecific antibody compounds can be used a modulators of target molecules, including CD3, PSMA, CD19, CXCR5, CD33, PDL1, VEGFR2, cMet, or Axl, and are useful in the treatment of one or more conditions.

Abstract: Provided are bispecific conjugates having the general formula: pharmaceutically acceptable salts thereof, pharmaceutical compositions thereof, and their use in the treatment of cancer.

Abstract: Provided are bispecific antibody compounds having the Formula I: wherein, FAB1, FAB2, and —X— are as defined herein. The provided bispecific antibody compounds can be used a modulators of target molecules, including CD3, PSMA, CD19, CXCR5, CD33, PDL1, VEGFR2, cMet, or Axl, and are useful in the treatment of one or more conditions.

Abstract: The present invention provides programmable universal cell receptors (PUCRs) comprising a catalytic antibody region, a transmembrane domain and a cytoplasmic domain. The PUCRs disclosed herein may be conjugated to a specificity agent in order to program the receptor for specificity to any molecule of interest. Also provided are nucleic acids encoding such PUCRs, and cells expressing the PUCRs. Such cells may be used in treating a variety of medical conditions and diseases including cancer and infectious diseases.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.