Abstract: An analog-to-digital converter macrocell architecture is provided with digital logic for accumulating code-density data for dynamic characterization of the converter. Each macrocell includes an A/D converter (10), a comparator (12), a bin counter (14), a clock counter (16), and a histogram counter (18). the code output of the A/D converter (10) is compared in the comparator (12) with the output of the bin counter (14) and each match increments the histogram counter (18). The histogram counter (18) accumulates code-density data for A/D converter dynamic characterization, these data being read once for every cycle of the clock counter (16).