Abstract: A method and related system provides an array of sensing elements located in rows and columns, and each column of sensing elements has a connected circuit chain which processes the signals from the sensing elements in that column. Each circuit chain produces a signal with a corrective gain value calculated for it relative to the datum of the array which is selected for the point where signal strength would be strongest. The method and device is capable of being used in a starring or scanning type array mode.

Abstract: An IR focal plane array (IR-FPA) includes an IR radiation detector (11a) having a plurality of IR radiation responsive photodetectors (PDs) and a readout integrated circuit (11) that includes a plurality of unit cells arranged in an N.times.M matrix. Each unit cell has an input coupled to an output of one of the IR radiation responsive photodetectors. The IR-FPA further includes M column amplifiers, preferably CTIAs, individual ones of which have an input that is coupled through one of N switches (.phi.tr) to individual ones of the N unit cells. A charge integrating capacitance in each unit cell is formed by a charge well underlying one (.phi..sub.1) of a plurality of transfer gates coupled between individual ones of the N unit cells that are coupled to one of the M column amplifiers.

Abstract: An improved imaging technique is disclosed wherein an output from an IR-FPA (16) corresponds to image motion, wherein a scene image stays correlated with the IR-FPA readout, and wherein non-uniformities (e.g., fixed pattern spatial noise) are uncorrelated from frame to frame. The uncorrelated fixed pattern spatial noise is identified and removed by a signal processor, such as a SB-NUC block (24). The scene image is scanned over the IR-FPA by a dither mirror (14) in synchronism with the movement of a frame of pixels (17) on the IR-FPA. Electronics (16a, 16b, 30, 32, 34) are included on the IR-FPA for controlling the scanning and read out of pixels within a currently selected frame.

Abstract: An adaptive dynamic range control circuit architecture is disclosed that enables an IR-FPA (10) to achieve a higher dynamic range. The circuit architecture significantly reduces a resolution required for an analog-to-digital converter (ADC 24) that converts the analog output signals of the IR-FPA to a digital representation. In a preferred embodiment of this invention a column CTIA readout integrated circuit architecture is used in conjunction with the adaptive feedback circuitry of this invention to provide pedestal suppression on a per-pixel basis for the IR-FPA. The use of the circuitry of this invention modifies the conventional column CTIA amplifier configuration to a configuration having an auto-zeroed charge ratioed gain stage (50). One advantage to this technique is that by suppressing the charge pedestal, the usable signal output from the IR-FPA can be brought off-chip to the readout integrated circuit at a much higher gain.