Abstract: Methods of heterogeneous crystallization and related systems are provided. In some embodiments, a method comprises crystallizing an agent in a suspension comprising a heteronucleant and the dissolved agent. Crystallization may occur on the surface of the heteronucleant with little or no bulk crystallization and/or secondary nucleation. In some embodiments, a crystallizer may be configured to inhibit secondary nucleation and/or bulk crystallization, for example, by reducing the formation of free crystals that may serve as nucleation surfaces while allowing for adequate mass and heat transfer. In some such embodiments, the crystallizer may be designed to flow (e.g., continuously) a suspension comprising a heteronucleant and an agent in a fluidized state. The methods and systems of the present invention may be used in a wide variety of applications, including the crystallization of pharmaceutically active agents.

Abstract: Inter alia, methods, and means for automatically generated travel expense reports. One embodiment identifies an email extractor that reads travel expense information from travel reservation booking emails. The extracted information is then displayed in electronic table format. The displayed information includes travel expense details such as vendor name, trip conveyance, date of reservation/expense, accommodation name, cost, currency, etc. The expense report can be accessed and edited by the user, if desired. The user can view and download the report in other formats, such as a spreadsheet.

Abstract: Inter alia, methods, and means for tracking frequent flyer miles. One embodiment identifies a user database which has a one to many relationship to an accommodations database which contains flights the user has taken along with the corresponding distance traveled in that flight. The distance traveled corresponds to the frequent flyer miles that have been earned for that flight. There is further a vendors database which contains the vendors with which the accommodation occurred with, along with an accommodations_vendors database which indicates which accommodation corresponds to which vendor. With these databases, on a per user basis, the number of frequent flyer miles per user per vendor can be determined. Two other databases allow the determination of the number of frequent flyer miles that can be redeemed for a given vendor based on the number of frequent flyer miles earned on the vendor partners of a given vendor. These two databases are the partners database and the partners_vendors database.

Abstract: Inter alia, methods, and means for price comparisons for travel and accommodations. One embodiment identifies an online database where users input the actual prices paid for travel services and accommodations, including any discounts, coupons, or price premiums. The database can be searched by all uses who have subscribed to the service. In one embodiment, the search criteria can any combination of vendor name, travel dates, start and end locations, booking date, flight number, etc. The users can thus determine the prices actually paid by other users for a given travel service or accommodation. This information could be valuable in negotiation better prices from vendors, or in determining if there are better times to make travel bookings.

Abstract: A buffing pad. The buffing pad includes a pad support having a first surface and a second surface; and a resilient foam pad having an attachment surface and a buffing surface, the attachment surface of the resilient foam pad secured to the first surface of the pad support, the resilient foam pad comprising at least two separate concentric rings of resilient foam, the concentric rings being positioned so that there is a gap therebetween. A method of making the buffing pad is also disclosed.

Abstract: Token buckets are used in a computer or communications system for controlling rates at which corresponding items are processed. The number of tokens in a token bucket identifies the amount of processing that is available for the corresponding item. Instead of storing the value of a token bucket as a single value in a single memory location as traditionally done, the value of a token bucket is stored across multiple storage locations, such as in on-chip storage and in off-chip storage (e.g., in a memory device). An indication (e.g., one or more bits) can also be stored on chip to identify whether or not the off-chip stored value is zero and/or of at least of a certain magnitude such that it may be readily determined whether there are sufficient tokens to process an item without accessing the off-chip storage.

Abstract: A single in-line memory module (SIMM) for memory expansion in a computer system. The SIMM includes a plurality of memory chips surface-mounted on a printed circuit board. The printed circuit board includes a dual read-out connector edge adapted for insertion within a socket of the computer system. One or more driver chips may further be mounted on the printed circuit board and connected to distribute control signals to the memory chips. A full-width data path may further be connected between the dual read-out connector edge and the plurality of memory chips.

Abstract: The system of the present invention provides for the verification and testing of electrical circuits and the generation of the information necessary to interface with computer aided testing equipment to physically test the fabricated circuits. The verification of the circuit is divided into two portions, functional verification and timing verification. Information generated during the verification process using the separate functional and timing verification information are then combined into a core structure from which test vectors are generated in a format compatible with a circuit testing apparatus which physically tests the fabricated circuit. In this format, unit delays previously employed to perform the timing tests are adjusted according to the timing specifications of the components to comply with the setup and hold times specified. Using this process, the test vectors required by the physical test apparatus to physically test a fabricated circuit are generated.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual read-out connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM, at a time to provide memory expansion in full width increments.

Abstract: An improved attachment mechanism for attaching the motherboard in a computer system to its chassis is disclosed. The attachment mechanism includes a rail that engages at least two opposing edges of the motherboard and a hook mechanism that engages a catch formed in the chassis. The hook mechanism is secured to a central portion of the motherboard. The rail and hook mechanism cooperate to securely couple the motherboard to the chassis without requiting the use of extensive usable space on the motherboard. The described arrangement permits the motherboard to be quickly and easily installed and released.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual read-out connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions.

Abstract: A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.

Abstract: An improved high speed, high density Dynamic Random Access Memory (DRAM) electrical signal interconnect structure which has particular application to computer systems which employ Single In-line Memory Modules (SIMMs). The structure contains an on-board buffer for driving time critical signals from a single source and further includes innovative signal trace routing having approximately equivalent minimum distance signal line lengths and vias to memory modules on the front and back surfaces of the circuit board resulting in a high speed, high density SIMM with clean rising/falling signal edges.

Abstract: A modular circuit board placement system is disclosed that provides for flexible placement of daughterboards, for minimal bus signal path lengths between motherboard and daughterboards, and for ease of installation and removal of daughterboards. The placement system employs dual height bus connectors, a stepped back panel, easy to engage and disengage dual height card retainers, filler panels that also function as module mounts, and multipurpose circuit card handles that facilitate removal of daughterboards. Daughterboards have a two-tier staggered arrangement above the motherboard. Each daughterboard has a signal transfer end that electrically connects to the motherboard through one of the dual height bus connectors, and a back panel connector end that couples to the back panel with an accessory connector or with a filler panel that functions as an electromagnetic interference shield.