Patents by Inventor James Thomas Brady
James Thomas Brady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6192482Abstract: An attached storage media link has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a high speed, cost effective interface to a direct access storage device.Type: GrantFiled: June 17, 1994Date of Patent: February 20, 2001Assignee: International Business Machines CorporationInventors: Daniel Francis Casper, James Thomas Brady, Robert Stanley Capowski, Frederick John Cox, Frank David Ferraiolo, Marten Jan Halma, Benjamin Hong Wu
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Patent number: 6101194Abstract: Conflicts are resolved between competing nodes in a multi-node communications network. After a first node in the network requests an initiation of communications with a target node, the requesting node may simply initiate the requested communications with the target node if the target node is not busy. If the first node determines that the target node is busy, it proceeds to resolve the conflict. Namely, the first node repeats the process of waiting for a first delay then requesting initiation of communications with the target node. After each unsuccessful attempt, the first delay is successively increased. As an example, the delay may be increased exponentially, with a controlled randomness added. After a or more queued messages to other nodes. Following this, the first node performs another sequence to initiate communications with the target node, successively increasing the delay between unsuccessful attempts, as before.Type: GrantFiled: June 9, 1997Date of Patent: August 8, 2000Assignee: International Business Machines CorporationInventors: Narasimha Lakshmi Annapareddy, James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Jai M. Menon, David Ronald Nowlen
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Patent number: 5940612Abstract: A procedure controls execution of priority ordered tasks in a multi-nodel data processing system. The data processing system includes a node with a software-controlled processor and a hardware-configured queue-controller. The queue-controller includes a plurality of priority-ordered queues, each queue listing tasks having an assigned priority equal to a priority order assigned to the queue.Type: GrantFiled: September 27, 1995Date of Patent: August 17, 1999Assignee: International Business Machines CorporationInventors: James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Noah R. Mendelsohn, Jaishankar Moothedath Menon, David R. Nowlen
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Patent number: 5860088Abstract: A method enables a host processor, which employs variable length (VL) records, to transparently communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records.Type: GrantFiled: December 6, 1996Date of Patent: January 12, 1999Assignee: International Business Machines CorporationInventors: Michael T. Benhase, James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Donald J. Lang, Jaishankar Moothedath Menon
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Patent number: 5857213Abstract: A method enables a host processor, which employs variable length (VL) records, to communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records.Type: GrantFiled: December 6, 1996Date of Patent: January 5, 1999Assignee: International Business Machines CorporationInventors: Michael T. Benhase, James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Donald J. Lang, Jaishankar Moothedath Menon
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Patent number: 5832204Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.Type: GrantFiled: June 23, 1997Date of Patent: November 3, 1998Assignee: International Business Machines CorporationInventors: Norman Apperley, James Thomas Brady, Steven Gerdt, Alden B. Johnson
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Patent number: 5832199Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.Type: GrantFiled: June 23, 1997Date of Patent: November 3, 1998Assignee: International Business Machines CorporationInventors: Norman Apperley, James Thomas Brady, Steven Gerdt, Alden B. Johnson
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Patent number: 5815650Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.Type: GrantFiled: June 23, 1997Date of Patent: September 29, 1998Assignee: International Business Machines CorporationInventors: Norman Apperley, James Thomas Brady, Steven Gerdt, Alden B. Johnson
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Patent number: 5808607Abstract: A multi-node video server system in accordance with the invention comprises disk storage associated with a first node which stores at least a portion of a video presentation in the form of plural data blocks, each data block comprising a viewing time segment of the presentation. RAM buffer in a second node receives and stores data blocks of the video presentation from the disk storage in the first node, upon an initial request by a first viewing terminal to view a portion of the video presentation. A communication module in the second node outputs the data blocks, as an isochronous data stream, to requesting terminals. A host controller is coupled to the video server nodes and receives requests from viewing terminals for the video presentation. The host controller causes the communication module in the second node to connect to a viewing terminal which renders the initial request.Type: GrantFiled: April 7, 1995Date of Patent: September 15, 1998Assignee: International Business Machines CorporationInventors: James Thomas Brady, Linda Marie Duyanovich, Boris Klots
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Patent number: 5784698Abstract: An apparatus for dynamically allocating memory includes a processor, a free buffer pool memory and a control memory which stores control block data structures. The control block data structures enable a segmentation of the free buffer pool memory into a series of free buffer pools, each free buffer pool comprising plural identical size buffers, each succeeding free buffer pool including a larger buffer size than a preceding free buffer pool. A selection size parameter for a given free buffer pool is a value that is larger than the buffer size comprising the given free buffer pool, but less than a next larger buffer size in the next of the series of free buffer pools.Type: GrantFiled: December 5, 1995Date of Patent: July 21, 1998Assignee: International Business Machines CorporationInventors: James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Noah R. Mendelsohn, Jaishankar Moothedath Menon, David R. Nowlen
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Patent number: 5758050Abstract: A system for managing data storage devices of a data storage subsystem. A data storage system includes a controller coupled to multiple data storage devices. In response to a request, the controller allocates the devices' storage space into a number of storage partitions or "virtual devices." The request specifies the size and function mode for each storage partition. Each storage partition, having the requested size, is operated according to its requested function mode. This involves mapping access commands, which specify virtual addresses, to the proper physical addresses of the appropriate data storage devices.Type: GrantFiled: March 12, 1996Date of Patent: May 26, 1998Assignee: International Business Machines CorporationInventors: James Thomas Brady, Paul T. Burton, Alden B. Johnson, Jaishankar Moothedath Menon, Steven Gerdt
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Patent number: 5727144Abstract: In a data processing system employing a disk array, prediction of a possible failure of a disk drive initiates copying of the data away from the potentially failing disk drive to a spare disk drive before the failing drive actually fails. If the disk drive does fail before the copying of the contents to a spare disk drive is completed, rebuilding of the remaining contents within the failing disk drive is performed.Type: GrantFiled: July 12, 1996Date of Patent: March 10, 1998Assignee: International Business Machines CorporationInventors: James Thomas Brady, Jaishankar Moothedath Menon
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Patent number: 5717850Abstract: Predictive failure analysis of a storage subsystem is efficiently conducted and data quickly recovered from a failed Read operation. This may be implemented in a storage system including a host coupled to a supervising processor that couples to a parity-equipped RAID storage subsystem having multiple HDAs each including an HDA controller and at least one storage medium. In one embodiment, when an HDA experiences an error during a Read attempt, the HDA transmits a recovery alert signal to the supervising processor; then, the processor and HDA begin remote and local recovery processes in parallel. The first process to complete provides the data to the host, and the second process is aborted. In another embodiment, an HDA's PFA operations are restricted to idle times of the HDA. A different embodiment limits HDA performance of PFA to times when the processor is conducting data reconstruction.Type: GrantFiled: March 12, 1996Date of Patent: February 10, 1998Assignee: International Business Machines CorporationInventors: Norman Apperley, James Thomas Brady, Steven Gerdt, Alden B. Johnson
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Patent number: 5717862Abstract: A multi-nodal data processing system includes a plurality of processing nodes, each node connected to plural other nodes by bidirectional data links. Each node comprises receivers for receiving messages on bidirectional data links and transmitters for transmitting messages on bidirectional data links. Each node records child nodes to which a message was transmitted and is further adapted to transmit a lock-up message received from a child node to a parent node, the lock-up message indicating a successful establishment of a message signal path to a destination node. Each node further is adapted to transmit a link cancel signal to another node to close the link in the event of an unsuccessful message transfer attempt over the link. Each node inhibits transmission of a lock-up signal to a parent node until link cancel signals have been received from all child nodes (other than a node from which a lock-up signal was received).Type: GrantFiled: April 27, 1995Date of Patent: February 10, 1998Assignee: International Business Machines CorporationInventors: Narasimhareddy L. Annapareddy, James Thomas Brady, Damon W. Finney, Richard F. Freitas, Michael Anthony Ko, Michael James Rayfield
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Patent number: 5675736Abstract: A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line.Type: GrantFiled: July 24, 1996Date of Patent: October 7, 1997Assignee: International Business Machines CorporationInventors: James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Paul Wayne Hunter, Michael Anthony Ko, Donald J. Lang, Noah R. Mendelsohn, Jaishankar Moothedath Menon, David Ronald Nowlen
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Patent number: 5671390Abstract: A method and means are disclosed in a Log Structure Array (LSA) storage subsystem for managing said subsystem without a need for an access to a complete LSA directory in a RAM. This object is achieved by maintaining (1) a subset of the LSA directory (referred to as LSA sub-directory) in a RAM where the LSA sub-directory comprises the logical track address of a predetermined number of most recently accessed logical tracks; (2) a journal of changes to the LSA directory which is maintained on a different power boundary than the LSA directory power boundary; and, (3) an array of bit maps, one bit map per segment which is used for fast garbage collection thus eliminating the need for having an access to a complete LSA directory in a RAM during garbage collection.Type: GrantFiled: May 23, 1995Date of Patent: September 23, 1997Assignee: International Business Machines CorporationInventors: James Thomas Brady, Alden B. Johnson, John Chi-Shing Lui, Jaishankar Moothedath Menon, Shin-Yuan Tzou