Patents by Inventor James Tomassetti
James Tomassetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8296121Abstract: Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system.Type: GrantFiled: April 25, 2007Date of Patent: October 23, 2012Assignee: Cadence Design Systems, Inc.Inventors: Mitchell G. Poplack, William F. Beausoleil, Tung-Sun Tung, James Tomassetti
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Patent number: 8160862Abstract: Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system during an emulation cycle. Power of the unused resources is controlled during emulation of a design under verification corresponding to the logic design by the emulation system. The resources may be identified as being unused during one or more steps of the emulation cycle. The power of the unused resources may be controlled by at least one of: powering down one or more of the unused resources; disabling one or more of the unused resources; freezing inputs to one or more of the unused resources; or setting inputs to one or more of the unused resources to a constant state. In this manner, power consumption of the emulation system is reduced.Type: GrantFiled: December 5, 2007Date of Patent: April 17, 2012Assignee: Cadence Design Systems, Inc.Inventors: Mitchell Grant Poplack, William F. Beausoleil, N. James Tomassetti, Tung-sun Tung
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Publication number: 20080270105Abstract: Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Applicant: Cadence Design Systems, Inc.Inventors: Mitchell Grant Poplack, William F. Beausoleil, N. James Tomassetti, Tung-sun Tung
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Patent number: 7047179Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.Type: GrantFiled: June 11, 2003Date of Patent: May 16, 2006Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, N. James Tomassetti
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Patent number: 6774475Abstract: A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.Type: GrantFiled: January 24, 2002Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Edmund D. Blackshear, William F. Beausoleil, N. James Tomassetti
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Publication number: 20030212539Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.Type: ApplicationFiled: June 11, 2003Publication date: November 13, 2003Applicant: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, Tak-Kwong Ng, Helmut Roth, Peter Tannenbaum, N. James Tomassetti
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Patent number: 6618698Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.Type: GrantFiled: August 12, 1999Date of Patent: September 9, 2003Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, N. James Tomassetti
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Publication number: 20030137041Abstract: A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.Type: ApplicationFiled: January 24, 2002Publication date: July 24, 2003Applicant: International Business Machines CorporationInventors: Edmund D. Blackshear, William F. Beausoleil, N. James Tomassetti
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Patent number: 6491205Abstract: Chips requiring high temperature reflow for attachment to a module substrate are attached first and then a eutectic water soluble solder paste and/or water soluble flux is dispensed on both the TSOP and the PBGA chip pads instead of using the paste screening techniques. The dispensing is done by injecting solder on the solder sites individually. Characteristics of the solder paste used is that it must be fluid enough to be injected onto the individual sites yet have enough body that it remains in place and does not run from site to site once dispensed. A paste capable of providing such characteristics is one having: a ) a very fine particle size in the range of 400 to 500 mesh and preferably between 400 and 450 mesh; b) a low viscosity (below 500 k centerpoise and preferably between 425 to 375 cps); and c) a solid content of 86% or lower and preferably between 84 and 80%.Type: GrantFiled: September 21, 2001Date of Patent: December 10, 2002Assignee: International Business Machines CorporationInventors: Chon C. Lei, Jac A. Burke, William F. Beausoleil, N. James Tomassetti, Lawrence A. Thomas, Tak-kwong Ng, Michael Kessler