Abstract: Two-stage force multiplier tin snips are provided which have a pair of cutting blades and associated tangs, both being pivotable about a cutting axis. Each respective tang is coupled to a pair of handles by a pair of respective tang pins. The handles are pivotably attached to one another about an adjustable handle axis. The handle axis is adjustable between an upper position and a lower position to provide a mechanism for changing a force multiplier of the cutting blades. The handle axis may be a sliding axis disposed in longitudinal slots on the handles. The handle axis may also be upper and lower fixed pins that are slidable in lateral slots.

Abstract: Two-stage force multiplier tin snips are provided which have a pair of cutting blades and associated tangs, both being pivotable about a cutting axis. Each respective tang is coupled to a pair of handles by a pair of respective tang pins. The handles are pivotably attached to one another about an adjustable handle axis. The handle axis is adjustable between an upper position and a lower position to provide a mechanism for changing a force multiplier of the cutting blades. The handle axis may be a sliding axis disposed in longitudinal slots on the handles. The handle axis may also be upper and lower fixed pins that are slidable in lateral slots.

Abstract: Vertical-color-filter pixel sensors having simplified wiring and reduced transistor counts are disclosed. In an embodiment, a single line is used for reference voltage, pixel reset voltage, and column-output signals in a VCF pixel sensor. In another embodiment, row-reset signals and row-enable signals are sent across a line that is shared between adjacent rows in an array of VCF pixel sensors. The present invention also provides an optimized layout for a VCF pixel sensor with shared row-reset, row-enable, reference voltage and column-output lines as well as a VCF pixel sensor in which source-follower voltage, source-follower amplifier voltage and row-enable signals all share a common line. These combined line embodiments can be used with a single column-output line as well as two row-enable lines. The embodiments can also be implemented in a VCF pixel sensor without a row-enable transistor.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: Vertical-color-filter pixel sensors having simplified wiring and reduced transistor counts are disclosed. In an embodiment, a single line is used for reference voltage, pixel reset voltage, and column-output signals in a VCF pixel sensor. In another embodiment, row-reset signals and row-enable signals are sent across a line that is shared between adjacent rows in an array of VCF pixel sensors. The present invention also provides an optimized layout for a VCF pixel sensor with shared row-reset, row-enable, reference voltage and column-output lines as well as a VCF pixel sensor in which source-follower voltage, source-follower amplifier voltage and row-enable signals all share a common line. These combined line embodiments can be used with a single column-output line as well as two row-enable lines. The embodiments can also be implemented in a VCF pixel sensor without a row-enable transistor.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: Ag system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.