Abstract: Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.

Abstract: An electronic package assembly wherein a low profile package is soldered to an organic (e.g., epoxy resin) substrate (e.g., printed circuit board). The assembly's projecting conductive leads are soldered. An encapsulant material (e.g., polymer resin) is used to provide reinforcement for the solder-lead connections, the encapsulant material being dispensed only along opposing sides of the package's housing which do not include projecting leads (and which are oriented substantially normal to the stresses imposed on the package during operation wherein high temperatures are attained). This dispensing may follow solder reflow and solidification. The invention is particularly useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.

Abstract: An electronic package assembly wherein a low profile package is soldered to an organic (e.g., epoxy resin) substrate (e.g., printed circuit board), the projecting conductive leads of the package and the solder which substantially covers these leads (and respective conductors on the substrate) having been substantially covered with encapsulant material (e.g., polymer resin) to provide reinforcement for the solder-lead connections. The encapsulant material is dispensed about the solder and lead joints following solder reflow and solidification so as to substantially surround the solder and any portions of the leads not covered with solder. The invention has particular useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.

Abstract: A method and apparatus for selectively spray etching an epoxy encapsulated chip which is mounted to a chip carrier without damage to the chip, the chip carrier or other closely mounted chips. The apparatus includes a diaphragm which can be raised and lowered to direct the flow of etchant solution at the encapsulating material located alongside and under the chip. The encapsulating material is removed from the chip without removing the chip from the chip carrier.

Abstract: A process for providing circuit lines on a substrate having a non-planar surface is provided. The process includes applying a layer of photoresist material to the substrate, selectively screen printing on non-planar areas of the substrate a screen-printable coating, photoprocessing the layer of photoresist material, and providing electrical conductive pattern on the substrate.