Patents by Inventor James V. Sherrill

James V. Sherrill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5040137
    Abstract: A finite impulse response filter that has the ability to use arbitrary TAPs that are essentially random access TAPs includes a plurality of circuits. The samples it operates on do not need to be a contiguous form. A sequencer is provided for counting up to a programmable number each time a start pulse is encountered and to provide an address and an incrementing address to a delta RAM, a coefficient RAM, and a micro code RAM. The delta RAM is used for storing the number of the TAP that is to be accessed. Delta Adders that directly follow the delta RAM are used with an input counter for making a ring counter for the input samples. A first and second sample RAM are used to hold incoming samples. An adder circuit is used for adding the output of the two sample RAMs to provide an output signal. A multiplier accumulator is connected to the adder circuit for receiving the output signal. The sequencer provides all the timing for the different cycles of the multiplier accumulator.
    Type: Grant
    Filed: December 13, 1989
    Date of Patent: August 13, 1991
    Assignee: Audio Animation
    Inventor: James V. Sherrill
  • Patent number: 4821208
    Abstract: A display processor, as for a small computer, processes pixel codes of various lengths. Three addressable color maps have their read addresses generated independently from portions of each pixel code. The portions of each pixel code used in generating each read address can be selected by programming.
    Type: Grant
    Filed: October 14, 1986
    Date of Patent: April 11, 1989
    Assignee: Technology, Inc.
    Inventors: Lawrence D. Ryan, James V. Sherrill, Robert D. Shedd, Gerald T. Caracciolo
  • Patent number: 4791580
    Abstract: A display processor for a computer with graphics capability includes color map memories addressed by portions of pixel codes during display line trace intervals. The read-outs from these color map memories provide the primary color component signals from which the drive signals for the display monitor kinescope are derived. The pixel codes, from which color map memory addresses are derived, are supplied at video rate to the display processor from the serial output port of dual-ported video random access memory. The color map memories are loaded with new color map data during display retrace intervals. By supplying this new color map data from the serial port of the dual-ported video random-access memory, the color map memories can be rapidly updated.
    Type: Grant
    Filed: October 14, 1986
    Date of Patent: December 13, 1988
    Assignee: Technology Inc. 64
    Inventors: James V. Sherrill, David L. Sprague