Abstract: A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.

Abstract: A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.

Abstract: A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.

Abstract: Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.

Abstract: An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: Alternative additives that can be used in place of isopropyl alcohol in aqueous alkaline etchant solutions for texturing a surface of a single-crystalline silicon substrate are provided. The alternative additives do not have volatile constituents, yet can be used in an aqueous alkaline etchant solution to provide a pyramidal shaped texture surface to the single-crystalline silicon substrate that is exposed to such an etchant solution. Also provided is a method of forming a textured silicon surface. The method includes immersing a single-crystalline silicon substrate into an etchant solution to form a pyramid shaped textured surface on the single-crystalline silicon substrate. The etchant solution includes an alkaline component, silicon (etched into the solution as a bath conditioner) and glycerol or ethylene glycol as an additive. The textured surface of the single-crystalline silicon substrate has (111) faces that are now exposed.

Abstract: Apparatus configured for the fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: Methods of fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: Alternative additives that can be used in place of isopropyl alcohol in aqueous alkaline etchant solutions for texturing a surface of a single-crystalline silicon substrate are provided. The alternative additives do not have volatile constituents, yet can be used in an aqueous alkaline etchant solution to provide a pyramidal shaped texture surface to the single-crystalline silicon substrate that is exposed to such an etchant solution. Also provided is a method of forming a textured silicon surface. The method includes immersing a single-crystalline silicon substrate into an etchant solution to form a pyramid shaped textured surface on the single-crystalline silicon substrate. The etchant solution includes an alkaline component, silicon (etched into the solution as a bath conditioner) and glycerol or ethylene glycol as an additive. The textured surface of the single-crystalline silicon substrate has (111) faces that are now exposed.

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: In a liquid crystal display device, a method for creating desirable pretilt angle by means of topography of the substrates, such as a surface that is sloped with respect to the surface of the electrodes. In combination with a low pretilt but highly photo-stable alignment layer, which may be very resistant to high levels of ultraviolet radiation, a high pretilt and photo-stable alignment structure is generated, by essentially combining two incompatible technical approaches. The ever more stringent requirements for projection displays are met. The methods for producing such sloped surfaces and the considerations related to design of the sloped surfaces are disclosed.

Abstract: A method of patterning magnetic devices and sensors by double etching, which includes forming a layer of dielectric on a substrate; depositing a thin adhesion layer and a thin seed layer; applying a thin resist frame to pattern a structure; cleaning the metal surface to prepare for plating; electroplating to fill up the structure and the uncovered field area, which uses a paddle cell with a permanent magnet providing magnetic field to induce magnetic orientation; stripping the resist frame; etching the seed layer/adhesion layer exposed below the resist frame down to the dielectric surface; etching the rest of magnetic materials and the seed layer using electrolytic etching in the field; etching the adhesion layer in the field, and repeating the steps for building structures with multiple levels.