Patents by Inventor James Victory

James Victory has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8762921
    Abstract: Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes receiving an optimization target specification; receiving an optimization parameter specification corresponding to an optimization parameter; receiving the target parameter; receiving a G-function corresponding to an ordered relationship representation; optimizing the optimization parameter specification as a function of the predetermined G-function; and producing at least one optimized geometric layout parameter (GLP) by the optimizing, wherein the at least one GLP corresponds to an optimized power cell.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Juan Cordovez, James Victory
  • Publication number: 20130311965
    Abstract: Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes receiving an optimization target specification; receiving an optimization parameter specification corresponding to an optimization parameter; receiving a the target parameter; receiving a G-function corresponding to an ordered relationship representation; optimizing the optimization parameter specification as a function of the predetermined G-function; and producing at least one optimized geometric layout parameter (GLP) by the optimizing, wherein the at least one GLP corresponds to an optimized power cell.
    Type: Application
    Filed: December 3, 2010
    Publication date: November 21, 2013
    Inventors: Juan Cordovez, James Victory
  • Patent number: 8204721
    Abstract: Predictive Split Lot Emulator, and methods simulating integrated circuit performance variations, before IC fabrication. The emulator receives a split lot parameter, maps the split lot parameter onto an IC element model, and transforms the IC element into a predictive IC element model. The emulator uses the predictive model to determine simulated performance characteristic of the IC element model. Also, a predictive split lot analyzer, a CAD simulation system, and a PDK including the emulator. IC simulating methods include choosing a Split Condition from a Split Table; a Predictive Split Lot Emulator receiving the Condition, determining a Split Parameter Condition Perturbation, mapping the Perturbation into a Model Parameter Perturbation for an IC element, and storing the Model Perturbation for an IC element into a Model Parameter Perturbation Library. The Perturbation Library emulates IC element performance characteristic in a Split Condition.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 19, 2012
    Assignee: Sentinel IC Technologies, Inc.
    Inventors: James Victory, Juan D. Cordovez
  • Publication number: 20100332208
    Abstract: Predictive Split Lot Emulator, and methods simulating integrated circuit performance variations, before IC fabrication. The emulator receives a split lot parameter, maps the split lot parameter onto an IC element model, and transforms the IC element into a predictive IC element model. The emulator uses the predictive model to determine simulated performance characteristic of the IC element model. Also, a predictive split lot analyzer, a CAD simulation system, and a PDK including the emulator. IC simulating methods include choosing a Split Condition from a Split Table; a Predictive Split Lot Emulator receiving the Condition, determining a Split Parameter Condition Perturbation, mapping the Perturbation into a Model Parameter Perturbation for an IC element, and storing the Model Perturbation for an IC element into a Model Parameter Perturbation Library. The Perturbation Library emulates IC element performance characteristic in a Split Condition.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 30, 2010
    Inventors: James Victory, Juan D. Cordovez
  • Patent number: 5411139
    Abstract: A keybox capable of being oriented in a horizontal or vertical position is disclosed. Keypanels are maintained in the keybox and may be secured in either a horizontal or vertical extended position for viewing. The keypanels are slidably mounted in grooved tracks thereby being located upright and parallel within the keybox. Upwardly extending keyhooks are located on the keypanels for retaining keys. The keypanels are square so that the keyhooks may be located extending upwardly when the keybox is oriented upwards or sidewards. The keypanels are accessible through an opening in the keybox and may be slid out of the keybox to an extended position through the opening. Each keypanel may be secured in a horizontal extended position on the keybox by locating a lower edge of the keypanel on a shoulder of the keybox and securing the keypanel thereon by locating a retaining bar coupled to the keybox in a notch in an upper edge of the keypanel.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: May 2, 1995
    Inventor: James Victory