Patents by Inventor James W. Bishop

James W. Bishop has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090323859
    Abstract: A flexible, reconfigurable, power efficient transmitter device and method is provided. In one embodiment, the method includes receiving outbound data and determining a mode of operation. When operating in a first mode the method may include modulation mapping the outbound data according a modulation scheme to provide first modulation mapped digital data, converting the first modulation mapped digital data to an analog signal that comprises an intermediate frequency (IF) analog signal, upconverting the IF analog signal to produce a first modulated radio frequency (RF) signal based on a local oscillator signal, upconverting the first RF modulated signal to produce a first RF output signal, and outputting the first RF output signal via an isolator.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 31, 2009
    Inventors: James W. Bishop, Nazrul H. Mohd Zaki, David Childress Newman, Steven N. Bundick
  • Publication number: 20090323854
    Abstract: A flexible, reconfigurable, power efficient transmitter device and method is provided. In one embodiment, the method includes receiving outbound data and determining a mode of operation. When operating in a first mode the method may include modulation mapping the outbound data according a modulation scheme to provide first modulation mapped digital data, converting the first modulation mapped digital data to an analog signal that comprises an intermediate frequency (IF) analog signal, upconverting the IF analog signal to produce a first modulated radio frequency (RF) signal based on a local oscillator signal, amplifying the first RF modulated signal to produce a first RF output signal, and outputting the first RF output signal via an isolator.
    Type: Application
    Filed: June 26, 2008
    Publication date: December 31, 2009
    Inventors: James W. Bishop, Nazrul H. Mohd Zaki, David Childress Newman, Steven N. Bundick
  • Publication number: 20090106538
    Abstract: The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 23, 2009
    Inventors: James W. Bishop, Hung Q. Le, Dung Q. Nguyen, Wolfram Sauer, Benjamin W. Stolt, Michael T. Vaden
  • Patent number: 6909854
    Abstract: An optical wireless communications system (1) comprises a server or transceiver hub (6) transmitting and/or receiving optical communications with geographically dispersed subscriber units (8) via optical beams. The transceiver hub (6) transmits a beam pattern that has an efficient, rectangular, flat-topped far field optical profile, thus permitting less complex and less expensive transceiver equipment to be employed in the transceiver hub (6) and in the subscriber units (8). In one embodiment, the transceiver hub (6) comprises an optical source (52, FIG. 3), an asymmetrical lens such as a cylindrical lens (60, FIG. 3), and a diffraction element such as a diffractive phase plate (65, FIG. 3). Various methods of shaping an optical transmission profile are also described.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: June 21, 2005
    Assignee: Motorola, Inc.
    Inventors: Norbert Kleiner, Diana C. Chen, James W. Bishop, Jr.
  • Patent number: 6415402
    Abstract: A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corporation
    Inventors: James W. Bishop, George A. Fax, Robert G. Iseminger
  • Publication number: 20010013111
    Abstract: A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.
    Type: Application
    Filed: January 24, 2001
    Publication date: August 9, 2001
    Applicant: International Business Machines Corporation
    Inventors: James W. Bishop, George A. Fax, Robert G. Iseminger
  • Patent number: 6219813
    Abstract: A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: April 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: James W. Bishop, George A. Fax, Robert G. Iseminger
  • Patent number: 5920882
    Abstract: A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory packages, allowing for elastic buffering of data in a variety of directions. Each programmable package includes package leads, a memory, and output drivers. Each output driver is connected to a respective package lead, which is configured to generate a logic function defined by programming data stored in the memory. A method includes storing programming data for operating the assembly to send signals on different paths between a programmable package and a memory package.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: July 6, 1999
    Assignee: TSI TelSys Inc.
    Inventors: Toby D. Bennett, James W. Bishop, Donald J. Davis, Jonathan C. Harris
  • Patent number: 5809396
    Abstract: A radio telecommunication network (10) includes satellites (12) which project cells (30) on the surface of the earth. Mobile units (16) are alerted to incoming calls when they receive ring signals. Ring signal coverage parameter values are selected in response to differentiating data (46) which cause different ring signals to be activated for mobile units (16) which appear to be proximately located. An illumination area ring signal coverage parameter may have a value selected in response to differentiating data (46) so that larger illumination areas are used for higher speed mobile units (16"). A transmission power ring signal coverage parameter may have a value selected in response to differentiating data (46) so that higher power ring signals are used in specific situations identified by the differentiating data (46).
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: September 15, 1998
    Assignee: Motorola, Inc.
    Inventors: Peter J. Armbruster, Dean Paul Vanden Heuvel, James W. Bishop, Jr.
  • Patent number: 5596624
    Abstract: A local exchange with limited access to outside communication systems is coupled to a global satellite communication system by a mobile exchange unit. The mobile exchange unit (MXU) provides access to the local exchange by relating one channel in the global communication system to many possible destinations in the local exchange. Multiple circuits of the local exchange are associated with a single mobile number. A gateway associated with the MXU associates an available radio channel with the calling subscriber. Multi-stage dialing is eliminated and a subscriber can directly dial a number of a party in the local exchange.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: January 21, 1997
    Assignee: Motorola, Inc.
    Inventors: Peter J. Armbruster, James W. Bishop, Jr.
  • Patent number: 5539895
    Abstract: A hierarchical cache system comprises a plurality of first level cache subsystems for storing data or instructions of respective CPUs, a higher level cache subsystem containing data or instructions of the plurality of cache subsystems, and a main memory coupled to the higher level cache subsystem. A page mover is coupled to the higher level cache subsystem and main memory, and responds to a request from one of the CPUs to store data into the main memory, by storing the data into the main memory without copying previous contents of a store-to address of the request to the higher level cache subsystem in response to said request. Also, the page mover invalidates the previous contents in the higher level cache subsystem if already resident there when the CPU made the request. A buffering system within the page mover comprises request buffers and data segment buffers to store a segment of predetermined size of the data.
    Type: Grant
    Filed: May 12, 1994
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: James W. Bishop, Charles E. Carmack, Jr., Patrick W. Gallagher, Stefan P. Jackowski, Gregory R. Klouda, Robert D. Siegl
  • Patent number: 5539875
    Abstract: In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: James W. Bishop, Mark L. Ciacelli, Patrick W. Gallagher, Stefan P. Jackowski, Gregory R. Klouda, Robert D. Siegl
  • Patent number: 5523997
    Abstract: A communication network (10) includes a constellation of satellites (12) in orbit around the earth. Gateways (14) communicate with the satellites (12), reside on the surface of the earth, and interface the network (10) to the local PSTN (18). User units (16) communicate with satellites (12) and provide communication services to users. A gateway (14) includes a mobile switching center (22), which connects half-calls, and an earth terminal controller (20), which occasionally overrides connections defined in the mobile switching center (22). When possible, communication paths connected at the mobile switching center (22) are intraswitched at a satellite (12) rather than being routed through the mobile switching center. However, when supplementary services are requested, the communication path is reconfigured back to the mobile switching center (22) so that additional signals may be inserted into the communication path.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: June 4, 1996
    Assignee: Motorola, Inc.
    Inventor: James W. Bishop, Jr.
  • Patent number: 5509004
    Abstract: A communication network (10) includes a constellation of satellites (12) in orbit around the earth. Gateways (14) communicate with the satellites (12), reside on the surface of the earth, and interface the network (10) to the local PSTN (18). User units (16) communicate with satellites (12) and provide communication services to users. A gateway (14) includes a mobile switching center (22), which connects half-calls, and an earth terminal controller (20), which occasionally overrides connections defined in the mobile switching center (22). When possible, communication paths connected at the mobile switching center (22) are intraswitched at one or more satellites (12) rather than being routed through the mobile switching center. However, when supplementary services are requested, the communication path is reconfigured back to the mobile switching center (22) so that additional signals may be inserted into the communication path.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: April 16, 1996
    Assignee: Motorola, Inc.
    Inventors: James W. Bishop, Jr., Peter J. Armbruster