Abstract: A high speed low power logic circuit, said logic circuit having at least first and second input terminals and an output terminal, said logic circuit accepting first and second binary inputs, respectively, at said first and second input terminals and providing a binary output at said output terminal, said binary output being a predetermined logical function of said first and second binary inputs, said logic circuit comprising: a first transistor, a second transistor and a first resistor serially connected between a first source of potential and a second source of potential, said first transistor being of first conductivity type and having an emitter, base and collector, said second transistor being of a second conductivity type opposite to said first conductivity type and having an emitter base and collector; a capacitor connected in parallel with said first resistor; a second resistor connected between said base of said second transistor and said second source of potential; first connections means passively c