Abstract: A computer system includes a memory module. The memory module includes volatile memory, a non-volatile memory subsystem, a host port, and a dual-port buffer device. The dual-port buffer device synchronously couples the non-volatile memory subsystem and the host port to the volatile memory. The dual port buffer device includes routing logic to selectably route address information provided by the host port and the non-volatile memory subsystem to the volatile memory.

Abstract: A method for aiding use of a computer includes receiving a home base signal, and in response to the home base signal, transferring control of the computer to a user home base application.

Abstract: The invention is a computer interface with a hardwired button array on the computer chassis for simulating the apparatus of common consumer electronic devices. Each button of the array of buttons is connected to at least two wires, with the depression of a button causing an electrical connection between the corresponding two wires. The voltage on one of these wires is forced to a steady-state logic low, while the voltage on the other wire is allowed to float electrically free. Nonetheless, the second wire is at a steady-state high voltage due to that wire's connection through a pull-up resistor to a voltage source. Upon electrical connection, the wire that is floating free acquires a logic low voltage. In response, a line state detector sends an interrupt signal to a microprocessor, which transitions the voltage on the wires forced to a steady-state logic low from a logic low to a free floating state.

Abstract: The invention is a computer system with a button array on the computer chassis for simulating the operation of common consumer electronic devices. Each button of the array of buttons is hardwired to the system processor. Upon activation of one of these buttons, an interrupt signal is sent to the system processor. The system processor halts whatever it is doing, and subsequently identifies the activated button. A signal generator attached to the buttons then sends the system processor a second interrupt signal, such that upon exiting the handling of the first interrupt, the system processor is presented with a second interrupt. The system processor then handles the second interrupt. While handling this second interrupt, the system processor executes whatever function corresponds to the activated button. The system processor then exits the handling of the second interrupt and resumes whatever activity it was engaged in before the activation of the button.