Abstract: In a communications receiver where the AGC signal derived from a phaselock detector is used to measure input signal strength, and that measurement is subject to error as a result of the nonlinear devices used in the carrier demodulation, a signal having inversely corresponding error characteristics is summed to the phaselock detector AGC signal to produce an improved AGC signal which is substantially linearly related to the input signal. That signal, having the inversely corresponding error characteristics, has been found to be the signal representation of the envelope of either the positive or negative cycles of the input signal.

Abstract: An assembly for attachment to a hollow ornament such as a Christmas tree ball having a cap adapted to fit over the open end or neck of the ornament, and defining a cut-out area. A clip having an elongated central portion and outwardly extending end portions, stop means located at each end of the central portion and teeth means interposed between the stop means and the outwardly extending end portions also comprises part of the assembly. The cap and clip are comprised of a flexible and bendable plastic material which is electrically non-conductive and fire resistant. The central portion of the clip extends in U-shape configuration through the cut-out area of the cap and the outwardly extending end portions of the clip engage the interior part of the hollow ornament beneath its open end. The stops are positioned above the cap and are of sufficient length compared to the cut-out area to prevent the central portion of the clip from falling through the cut-out area into the interior of the ornament.

Abstract: A radio receiver includes a phaselocked loop including a main phase detector which accomplishes both carrier extraction and demodulation of an FM orderwire signal. The loop bandwidth characteristic is made suitable for de-emphasis of the FM orderwire audio signal, and the output of a quadrature phase detector is applied as a divisor to an analog divider in the phaselocked loop to cause the bandwidth of the phaselocked loop to remain substantially constant despite changes in input signal level.

Abstract: A phaselock loop in a phaselock receiver includes a voltage-controlled oscillator, and a main phase detector receptive to an output of the oscillator and a received signal. Means to detect when the oscillator is phase locked with the received signal includes a quadrature phase detector receptive to a quadrature-phase-shifted oscillation from the oscillator and the received signal. Means are provided to subtract the direct-current component of the output of the main phase detector from the direct-current component of the output of the quadrature phase detector to provide a phaselock-indicating signal which is substantially zero when the oscillator is out-of-lock with the received signal, and which is high when the oscillator is in-lock with the received signal.