Patents by Inventor James W. Fuller, Jr.
James W. Fuller, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120247822Abstract: A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Applicant: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, JR., Jeffrey Knight, Voya R. Markovich, Kostas I. Papathomas
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Patent number: 7343674Abstract: A method of making a circuitized substrate assembly wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, and a cover is placed over one of the openings and a quantity of conductive paste is positioned thereon prior to bonding the substrates. At least some of the paste is then forced up into an opening in the other substrate as a result of the bonding.Type: GrantFiled: February 9, 2006Date of Patent: March 18, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
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Patent number: 7163847Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.Type: GrantFiled: October 26, 2005Date of Patent: January 16, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
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Patent number: 7091066Abstract: A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors.Type: GrantFiled: October 27, 2005Date of Patent: August 15, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
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Patent number: 7084014Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.Type: GrantFiled: October 7, 2003Date of Patent: August 1, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
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Patent number: 7071423Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: GrantFiled: August 11, 2004Date of Patent: July 4, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
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Patent number: 7047630Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: GrantFiled: March 30, 2004Date of Patent: May 23, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
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Patent number: 6900392Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: GrantFiled: September 3, 2004Date of Patent: May 31, 2005Assignee: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
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Patent number: 6872894Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: GrantFiled: March 6, 2003Date of Patent: March 29, 2005Assignee: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
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Patent number: 6832436Abstract: A method for forming a substructure or an electrical structure. To form the substructure, a sheet of conductive material having exposed first and second surfaces is provided. A hole is formed through the sheet of conductive material. A first layer of dielectric material is applied to the exposed first surface, after the forming the hole. No material was inserted into the hole before applying the first layer of dielectric material to the exposed first surface. To form the electrical structure, a multilayered laminate that includes a plurality of substructures is formed such that a dielectric layer insulatively separates each pair of successive substructures.Type: GrantFiled: March 7, 2002Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: Donald O. Anstrom, Bruce J. Chamberlin, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, Douglas O. Powell, Joseph P. Resavy, James R. Stack
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Patent number: 6809269Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: GrantFiled: December 19, 2002Date of Patent: October 26, 2004Assignee: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
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Patent number: 6781064Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.Type: GrantFiled: June 29, 1999Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Anilkumar C. Bhatt, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, William J. Rudik, William E. Wilson
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Patent number: 6529379Abstract: Providing a layer of ZnCr intermediate a dielectric substrate and a heat spreader enhances the adhesion between the dielectric substrate and heat spreader.Type: GrantFiled: October 13, 1998Date of Patent: March 4, 2003Assignee: International Business Machines CorporationInventors: James W. Fuller, Jr., Jeffrey A. Knight
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Patent number: 6407341Abstract: Conductive substructures of a multilayered laminate and associated methods of fabrication. The conductive substructures include a 0S1P substructure, a 0S3P substructure, and a 2S1P substructure, in accordance with the notation nSmP, wherein n and m are non-negative integers, wherein S stands for “signal plane,” and wherein P stands for “power plane.” A signal plane is characterized by its inclusion of a layer comprising conductive circuitry. A power plane is characterized by its inclusion of a continuously conductive layer. Thus, a 0S1P substructure includes 0 signal planes and 1 power plane (n=0, m=1). A 0S3P substructure includes 0 signal planes and 3 power plane (n=0, m=3) with a dielectric layer between each pair of power planes. A 2S1P substructure includes 2 signal planes and 1 power plane (n=2, m=1) with a dielectric layer between the power plane and each signal plane.Type: GrantFiled: April 25, 2000Date of Patent: June 18, 2002Assignee: International Business Machines CorporationInventors: Donald O. Anstrom, Bruce J. Chamberlin, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, Douglas O. Powell, Joseph P. Resavy, James R. Stack
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Patent number: 5981880Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.Type: GrantFiled: August 20, 1996Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, Anilkumar Chinuprasad Bhatt, James W. Fuller, Jr., John Matthew Lauffer, Voya Rista Markovich, William John Rudik, William Earl Wilson
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Patent number: 5869356Abstract: According to the present invention, a technique for controlling the flow of plastic encapsulant which is applied over an integrated circuit (I/C) chip wire bonded to wire pads formed on a chip carrier substrate is provided. This technique includes applying a barrier material to the substrate surrounding the wire bond pads, which barrier material is in the form of two walls projecting upwardly from the surface thereof, and defining a well between the walls to confine the flow of the encapsulant material. This prevents the encapsulant material from flowing past a desired defined boundary and covering the circuit connection pads which are not intended to be covered.Type: GrantFiled: March 17, 1998Date of Patent: February 9, 1999Assignee: International Business Machines CorporationInventors: James W. Fuller, Jr., Mary Beth Fletcher, Joseph Alphonse Kotylo, Jeffrey Alan Knight, David Michael Passante, Allen F. Moring
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Patent number: 5784260Abstract: According to the present invention, a technique for controlling the flow of plastic encapsulant which is applied over an integrated circuit (I/C) chip wire bonded to wire pads formed on a chip carrier substrate is provided. This technique includes applying a barrier material to the substrate surrounding the wire bond pads, which barrier material is in the form of two walls projecting upwardly from the surface thereof, and defining a well between the walls to confine the flow of the encapsulant material. This prevents the encapsulant material from flowing past a desired defined boundary and covering the circuit connection pads which are not intended to be covered.Type: GrantFiled: May 29, 1996Date of Patent: July 21, 1998Assignee: International Business Machines CorporationInventors: James W. Fuller, Jr., Mary Beth Fletcher, Joseph Alphonse Kotylo, Jeffrey Alan Knight, David Michael Passante, Allen F. Moring