Abstract: A low power radio transmitter includes an intermediate frequency stage, signal-to-pulse conversion module, and a power amplifier. The intermediate frequency stage up-converts the frequency of a base-band digital signal into an N-bit signal at the intermediate frequency. The signal-to-pulse conversion module converts the N-bit signal at the intermediate frequency into a pulse signal of M-bits at the radio frequency. As such, the signal-to-pulse conversion module is taking an N-bit signal (e.g., an 8-bit digital signal) and converting it into an M-bit pulse signal (e.g., a 1-bit pulse stream). Accordingly, the M-bit signal at the radio frequency is essentially a square-wave, which has a peak to average ratio of zero, is subsequently amplified by the power amplifier.

Abstract: A radio receiver includes a low-noise amplifier, pulse-to-signal conversion module, and intermediate frequency stage. The low-noise amplifier is operably coupled to receive and amplify an M-bit signal at a radio frequency. The M-bit signal at a radio frequency is representative of a pulse signal that is carried on a radio frequency. The pulse-to-signal conversion module demodulates the M-bit signal to produce an N-bit signal at an intermediate frequency. For example, the pulse-to-signal conversion module performs pulse-width demodulation, pulse-density demodulation, or pulse-position demodulation to recapture the N-bit signal. The intermediate frequency stage steps down the frequency of the N-bit signal to produce a base-band digital signal.

Abstract: The present invention relates to circuitry and an associated method for detecting a synchronization signal in a multi-media data transmission system. Preferably, the circuitry (10) includes process controller (40), memory (44), and a comparator (46). The process controller (40) controls the receipt of bit groups of data (52) and the storage of the bit groups of data (50) in the memory (44). The memory (44) operably couples to the process controller (40), receives the data, and stores the data in a predetermined order based upon the process controller (40). The comparator (46) couples to the process controller (40) and the memory (44) and compares the corresponding index locations of the bit groups (52) to a synchronization pattern (58). When the synchronization pattern (58) matches the predetermined set of bit groups (52), the comparator (46) generates the synchronization detection signal (60).

Abstract: A digital signal processor (10) for implementing a gain instruction. The gain instruction, when decoded, controls a multiplexer (43) to select a gain control index signal. The value of the chosen gain control index signal is added to a program control register (48) to produce a program address. The program address is used to choose one of four gain values specified by the gain instruction. The gain value is multiplied by a value accessed through an address indirect register, also specified by the instruction, and the result is stored in an accumulator.

Abstract: An instruction fetch and issuance unit (200) fetches two instruction words and issues at least one instruction word to an instruction decoder (250) per clock cycle. Two multiplexers (220, 230) receive the two fetched instructions and one or both of two of three words stored in an instruction register (240). A controller (210) selectively controls (207-209), in accordance with a state diagram (300), the loading of three words into the instruction register (240) from among the inputs of the multiplexers (220,230). The instruction register (240) issues up to two instructions per clock cycle without requiring the processor to stall to retrieve an additional word, allowing efficient issuance of a double-word instruction or two instructions in parallel.

Abstract: A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

Abstract: Data converter (10, 50, 150, 200) and method (250, 300) operate at variable sampling rates. Input gain stage (12) adjusts input bit stream (18) at an input bit rate (20) to produce gain adjusted bit stream (22). Integrator (14) and comb filter (16) operate on the gain adjusted bit stream (22) to produce a filtered bit stream (28) at an output bit rate (24). The gain of the integrator (14) and comb filter (16) pair varies with the sampling rates implemented. An input gain value of the input gain stage (12) adjusts to compensate for the gain of the integrator (14) and comb filter (16) pair to produce the filtered bit stream (28) within a predetermined dynamic range. DC offset stage (52) and output gain stage (54) provide further adjustment to the filtered bit stream (28). Data converters (10, 50) and method (250) convert data from a higher frequency bit rate to a lower frequency bit rate. Data converters (150, 200) and method (300) convert data from a lower frequency bit rate to a higher frequency bit rate.

Abstract: A method and apparatus for a multiply accumulate circuit (10) having a programmable saturation value is accomplished by providing saturation logic (20) that receives a saturation range signal (32) from a Digital Signal Processor (DSP) programmer. The saturation range signal (32) is then converted to a selected saturation value (34) and provided as an input to the saturation logic (20). The saturation logic (20) utilizes the selected saturation value (34) to establish an intermediate saturation value (30). For each intermediate resultant generated by the multiply and accumulate circuit (10), the intermediate resultant is compared with the intermediate saturation value (30). When the intermediate resultant compares unfavorably to the intermediate saturation value (30), a saturation default value (42) is supplied to the accumulator register. Additionally, the final accumulate result is compared against a final saturation value, and, if unfavorable, a saturation value is provided as the final result.

Abstract: A D/A converter (10) converts a digitized analog signal (32) to an analog signal (50). The D/A converter (10) includes first filtering stage (12), second filtering stage (14), and reduced-bit D/A converter (16). The first filtering stage (12) operates at a first sampling rate (25), interpolates the digitized analog signal (32) from an initial sampling rate to a first sampling rate (25), performs an anti-alias filter, and performs a first comb filtering function. The second filtering stage (14) operates at a second sampling rate (46), interpolates the digitized analog signal (32) to the second sampling rate (46), performs a second comb filtering function, and performs a noise shaper filter to produce a reduced-bit second sampling rate signal (48). The reduced-bit D/A converter (16) converts the second sampling rate signal (48) to an analog signal (50).

Abstract: A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

Abstract: A digital phase lock loop controller (DPLL) (10) incorporates an adjustment generator (34) for continually adjusting the sensitivity of the DPLL (10) to reduce injected noise. The DPLL also comprises an error detector (16), a frequency adjuster (22), a first oscillation generator (28), and a divider (32) that function in a manner common to many DPLLs (10). However, the adjustment generator (34) continually adjusts the operation of the frequency adjuster (22) based upon the relative phase difference between a reference oscillation (12) and a feedback oscillation (14) in order to vary the sensitivity of the DPLL (10). When the reference oscillation (12) and the feedback oscillation (14) are relatively in phase, the sensitivity of the DPLL (10) is low. Oppositely, when the reference oscillation (12) and the feedback oscillation (14) move out of phase, the sensitivity of the DPLL (10) increases.

Abstract: A digital phase lock loop (DPLL) (10) includes a first comparator (12), a second comparator (14), a third comparator (16), and adjuster (18), feedback divider (20), a threshold unit (21), a digital oscillator (23), and a loop filter (24). The first comparator (12), loop filter (24), digital oscillator (23), and feedback divider (20) of the DPLL (10) operate to produce a controlled oscillation. The second comparator (14), third comparator (16), and adjuster (18) provide a divisor to the feedback divider (20) that allows the DPLL (10) to operate with a variety of unknown system clock (22) frequencies.

Abstract: A data processing system for performing square operations includes a data processor such as a digital signal processor (DSP) and a memory system. The DSP has two data paths for fetching two operands of an instruction from locations specified by two addresses, which may be required for an operation such as a multiply operation. A fetch from the second data path is delayed in response to a wait signal. The memory system includes at least two memory portions. Data from the two memory portions are multiplexed onto the two data paths in response to a first portion of the respective addresses. If the first portions of both addresses are equal, and if second portions are unequal, the wait signal is activated. If the second portions of the addresses are equal, such as during a square operation, the wait signal is inactive and data is simultaneously read by both data paths.

Abstract: An apparatus for performing multiplications with reduced power includes an arithmetic logic unit and a decode block for performing an equivalent of a multiply instruction. A frequently-encountered multiply instruction occurs between a variable and a known constant. If the known constant is positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to zero, or subtract the variable from zero, in response to the sign bit of the known constant. In response to a multiply and accumulate instruction between a variable and a known constant of positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to the prior accumulated result or to subtract it therefrom, in response to the sign bit of the known constant. In either case, the high-speed multiplier is disabled and its power saved.

Abstract: An apparatus for performing multiplications with reduced power includes an arithmetic logic unit and a decode block for performing an equivalent of a multiply instruction. A frequently-encountered multiply instruction occurs between a variable and a known constant. If the known constant is positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to zero, or subtract the variable from zero, in response to the sign bit of the known constant. In response to a mulitply and accumulate instruction between a variable and a known constant of positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to the prior accumulated result or to subtract it therefrom, in response to the sign bit of the known constant. In either case, a high-speed multiplier is disabled and its power saved.