Abstract: An integrated circuit (IC) chip contains a small non-volatile “ID” memory such as an FeRAM array that stores information associated with manufacturing, testing, and performance of the IC chip. The stored information can include but is not limited to a serial number, a wafer ID, a batch ID, a date code, chip history, test data, and performance information. The storing information on the chip eliminates any difficulty in matching the information with the IC chip and provides a flexible permanent record of any information the manufacturer may find useful. The ID memory thus permits tracking and identification of ICs to a degree that was not previously practical. Additionally, a self-test can compare prior test results stored in the ID memory to current self-test results to detect defects or to select operating parameters of the integrated circuit.

Abstract: A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Abstract: A comparator-type sense amplifier compares a constant voltage that was read out of a FeRAM cell to a sequence of reference voltage levels. A multiple-comparison operation includes (a) reading out data to a bit line, (b) applying a first/next reference voltage, (c) comparing the bit line voltage to the applied reference voltage, and (d) repeating steps (b) and (c) one or more times. The multiple comparison operation can be used to characterize operation of an FeRAM cell, predict or detect an FeRAM cell that may introduce a bit error, or to read a multi-bit value from an FeRAM cell.

Abstract: A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Abstract: An integrated circuit (IC) chip contains a small non-volatile “ID” memory such as an FeRAM array that stores information associated with manufacturing, testing, and performance of the IC chip. The stored information can include but is not limited to a serial number, a wafer ID, a batch ID, a date code, chip history, test data, and performance information. The storing information on the chip eliminates any difficulty in matching the information with the IC chip and provides a flexible permanent record of any information the manufacturer may find useful. The ID memory thus permits tracking and identification of ICs to a degree that was not previously practical.

Abstract: An integrated circuit device includes a two-dimensional array of ferroelectric memory cells in which plate lines within the array are grouped. The grouping of plate lines accommodates the use of larger plate line drivers, such as CMOS driver inverters. Each plate line group may include some but not all of the rows of memory cells and some but not all of the columns of memory cells within the array.

Abstract: An integrated circuit device includes a two-dimensional array of ferroelectric memory cells in which plate lines within the array are grouped. The grouping of plate lines accommodates the use of larger plate line drivers, such as CMOS driver inverters. Each plate line group may include some but not all of the rows of memory cells and some but not all of the columns of memory cells within the array.

Abstract: A comparator-type sense amplifier compares a constant voltage that was read out of a FeRAM cell to a sequence of reference voltage levels. A multiple-comparison operation includes (a) reading out data to a bit line, (b) applying a first/next reference voltage, (c) comparing the bit line voltage to the applied reference voltage, and (d) repeating steps (b) and (c) one or more times. The multiple comparison operation can be used to characterize operation of an FeRAM cell, predict or detect an FeRAM cell that may introduce a bit error, or to read a multi-bit value from an FeRAM cell.

Abstract: A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.

Abstract: A sensing circuit with independent write-back capability includes a write back function block having a write-back output signal, a sense amplifier that receives an input and a reference signal. The sense amplifier generates an output signal and the write back function block further receives this output signal. An optional data buffer also receives the output signal.

Abstract: A sensing circuit with independent write-back capability includes a write back function block having a write-back output signal, a sense amplifier that receives an input and a reference signal. The sense amplifier generates an output signal and the write back function block further receives this output signal. An optional data buffer also receives the output signal.

Abstract: A multi-port memory with an array that is implemented without the additional signal lines and transistors usually found in prior multi-port memories. The multi-port memory includes a port control circuit that senses accesses from different ports and sequences the accesses to the array. The multi-port memory also includes an input/output structure for holding data associated with the accesses as they are sequenced.

Abstract: A system for testing the electrical conductivity of printed traces, on multiple surfaces, of a printed wiring board using non-contacting probes. The non-contact probes generate a plasma in a plasma generating chamber that is used to apply a voltage to the printed wiring board. A measurement circuit determines the magnitude of the voltage on the printed wiring board.

Abstract: A bipolar ink jet driver circuit includes a plurality of individual driver cells having a common collector and a resistive heater element. A common collector obviates the need for any isolation between adjacent driver cells. The driver cells each include two bipolar transistors configured as a Darlington pair, which drive an associated resistive heater element. The cells are grouped together to form individual driver circuits each having a control line for enabling each driver circuit. The cells within each driver circuit are individually addressable via address lines which are coupled to each of the driver elements. The resistive heater elements are actuated by enabling a driver circuit and addressing a driver cell within the enabled driver circuit.

Abstract: An integrated circuit pulse generator for per pin testing of electronic circuits. The pulse generator allows for independent adjustment of the slew rates of the rising and falling edges of the pulses. The pulse edges are generated by summing two separately controlled falling edge ramp generators. The circuit design of the pulse generator is structured to allow implementation with NPN transistors. The falling edge ramp generators operate by discharging a capacitor with a current source. The slew rates are varied by incrementally adding capacitance to the capacitor being discharged.

Abstract: A bipolar ink jet driver circuit includes a plurality of individual driver cells having a common collector and a resistive heater element. A common collector obviates the need for any isolation between adjacent driver cells. The driver cells each include two bipolar transistors configured as a Darlington pair, which drive an associated resistive heater element. The cells are grouped together to form individual driver circuits each having a control line for enabling each driver circuit. The cells within each driver circuit are individually addressable via address lines which are coupled to each of the driver elements. The resistive heater elements are actuated by enabling a driver circuit and addressing a driver cell within the enabled driver circuit.

Abstract: Pin electronics for an IC tester are built as an integrated circuit for characterizing the electrical operation of a device under test (DUT) by applying a test voltage to each of the pins on the DUT and measuring each resulting current. Typically, an IC tester selects one of several measure resistors, applies a stimulus to a pin of the DUT using an input driver, and measures the current response of the DUT through the related measure resistor. Each measure resistor corresponds to a specific current range and measurement accuracy is proportional to the precision of the selected resistor. Each measure resistor is a series of precision integrated resistors having a very low leakage current. This provides for current measurements of high sensitivity.

Abstract: Pin electronics for an IC tester are built as an integrated circuit for testing the electrical operation of a device under test (DUT) by applying a test voltage to each of the pins on the DUT and measuring each resulting current. The tester uses diode switches instead of discrete relays to switch between measurement ranges. Leakage current, on the order of nanoamperes from a switch that is open or disabled, is dramatically reduced by reverse biasing the diodes in each diode switch about the switch's diode bridge output node by an equal amount so that the summed current at the output node is almost zero.

Abstract: Pin electronics for an IC tester are built as an integrated circuit for testing the electrical operation of a device under test (DUT) by applying a test voltage to each of the pins on the DUT and measuring each resulting current. Typically, when the tester switches between the internal measure resistors, a voltage spike occurs on the pin of the DUT of a magnitude that may severely damage the sensitive circuitry on the DUT. Voltage spike suppression is included in the circuitry to minimize the effects on the DUT of voltage spikes.

Abstract: Pin electronics for an IC tester are built as an integrated circuit for characterizing the electrical operation of a device under test (DUT) by applying a test voltage to each of the pins on the DUT and measuring each resulting current. Typically, an IC tester selects one of several measure resistors, applies a stimulus to a pin of the DUT using an input driver, and measures the current response of the DUT through the related measure resistor. Each measure resistor corresponds to a specific current range and measurement accuracy is proportional to the precision of the selected resistor. Each measure resistor is a series of precision integrated resistors having a very low leakage current. This provides for current measurements of high sensitivity.