Patents by Inventor James W. Leith

James W. Leith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7612546
    Abstract: A voltage regulator includes a voltage source for providing an input voltage. The regulator includes circuitry responsive to the input voltage for generating a regulated output voltage. The circuitry enables selection of one of internal linear voltage regulation or external linear voltage regulation for generating the regulated output voltage.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: November 3, 2009
    Assignee: Intersil Americas Inc.
    Inventors: James W. Leith, Gustavo J. Mehas, Bogdan Duduman
  • Patent number: 7453251
    Abstract: A control circuit for a PWM switching power regulator including an error amplifier and an amplifier filter circuit. The error amplifier has a first input receiving a reference signal, a second input receiving an output sense signal, and an output providing a compensation signal used to control PWM switching. The amplifier filter circuit has an input receiving a ratio-metric tracking signal and an output providing the reference signal to the input of the error amplifier. The control circuit may include a resistive voltage divider for providing the tracking signal. The amplifier filter circuit may be implemented as a transconductance amplifier having an input receiving the tracking signal and an output coupled to a capacitor. The transconductance amplifier may have a relatively small current drive capacity and its output may have a relatively slow and weak response to changes of the tracking signal.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: November 18, 2008
    Assignee: Intersil Americas Inc.
    Inventors: Gustavo J. Mehas, James W. Leith, Shying D. Chen
  • Patent number: 7256623
    Abstract: A frequency programmable feed forward oscillator and triangular wave generator is disclosed having a first input for receiving an input voltage and a second input for receiving an input current. Circuitry within the device responsive to the input voltage scales the amplitude of a triangle wave form according to the provided input voltage and provides the scaled output voltage at a first output. In conjunction, the circuitry also generates a scaled PWM frequency responsive to the provided input current and provides this at a second output.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: August 14, 2007
    Assignee: Intersil Americas Inc.
    Inventors: Brandon D. Day, James W. Leith, Gustavo J. Mehas
  • Patent number: 7227731
    Abstract: Apparatus for providing over-current protection in a power converter device includes a first circuit for providing high-side sinking over-current protection for the power converter device responsive to a phase signal and a high-side over-current signal of the power converter device. A second circuit provides low-side sinking over-current protection for the power converter device responsive to the phase signal and the low-side over-current signal of the power converter device. Finally, a third circuit provides low-side sourcing over-current protection responsive to the phase signal, the low-side over-current protection signal and a power ground signal of the power converter device.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: June 5, 2007
    Assignee: Intersil Americas Inc.
    Inventors: James W. Leith, Gustavo J. Mehas, Brandon D. Day
  • Patent number: 7088600
    Abstract: An apparatus for reducing surge currents during startup of a voltage regulator is disclosed that includes circuitry for maintaining a voltage at an FB pin of the voltage regulator substantially equivalent to an output voltage of the voltage regulator.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 8, 2006
    Assignee: Intersil Americas, Inc.
    Inventors: Gustavo J. Mehas, James W. Leith, Brandon D. Day
  • Patent number: 7084613
    Abstract: A PWM system that minimizes output ripple of a multiphase DC-DC converter which converts N input voltages including at least one dissimilar input voltage. The PWM system includes PWM waveform logic that generates N PWM signals including a PWM signal for each of the N input voltages, and PWM control logic that optimizes relative phases of the N PWM signals based on voltage levels of the N input voltages. Various circuits and/or methods are contemplated for optimizing phase, including, for example, centering pulses for each PWM cycle, distributing pulses based on predetermined optimal phase angles, determining input voltage levels and selecting predetermined optimal phase angles, generating phase signals employing predetermined phase angles, measuring input voltages and calculating optimal phase angles, and using PLL logic or the like to measure and equalize off-times between PWM pulses.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: August 1, 2006
    Assignee: Intersil Americas Inc.
    Inventors: Matthew B. Harris, James W. Leith, Brandon D. Day
  • Patent number: 7038514
    Abstract: A startup circuit for a power converter including an amplifier circuit, a comparator, and startup logic. The power converter includes an error amplifier that compares an output sense signal with a startup reference signal and that provides a compensation signal. The amplifier circuit charges the startup reference signal to a predetermined reference level based on a second reference signal in response to a start signal. The comparator determines when the compensation signal reaches a predetermined ramp level and asserts a startup complete signal indicative thereof. The startup logic provides the start signal and provides an output enable signal in response to the startup complete signal. The output enable signal enables output switching to initiate normal regulation operation of the output voltage. In one embodiment, the predetermined ramp level is approximately the center voltage of a sawtooth regulation waveform used for PWM modulation.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: May 2, 2006
    Assignee: Intersil Americas Inc.
    Inventors: James W. Leith, Gustavo J. Mehas
  • Patent number: 7034586
    Abstract: A method of starting a DC—DC converter into a precharged output voltage including generating a reference voltage having a linear relationship with the output voltage such that the reference voltage ranges between a minimum and maximum voltage level of a PWM triangular waveform as the output voltage ranges between zero and an input voltage level, and enabling output switching of the DC—DC converter when the reference voltage is approximately equal to a compensation signal generated by an error amplifier comparing the reference voltage with a feedback signal representative of the output voltage. Generating a reference voltage may include applying a first current based on the input voltage through two resistors to develop the minimum and maximum voltage levels, applying the first current in one direction through a third resistor, and applying a second current based on the output voltage through the third resistor in the opposite direction.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: April 25, 2006
    Assignee: Intersil Americas Inc.
    Inventors: Gustavo J. Mehas, James W. Leith, Brandon D. Day
  • Patent number: 6975163
    Abstract: An IC including a margining control amplifier circuit, first and second offset pins, a margining control pin, select logic, and a mirror amplifier circuit. The margining control amplifier circuit drives current at an output to control voltage at an input based on a reference voltage. The first and second offset pins are provided to couple an external margining voltage divider. The margining control pin has at least two states including an up state and a down state. The select logic selectively switches the output of the margining control amplifier circuit between the first and second offset pins and selectively switches the input of the margining control amplifier circuit between the second and first offset pins based on a state of the margining control pin. The mirror amplifier circuit mirrors voltage across the first and second offset pins across a first margining resistor.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: December 13, 2005
    Assignee: Intersil Americas, Inc.
    Inventors: Gustavo J. Mehas, James W. Leith, Brandon D. Day
  • Patent number: 6340903
    Abstract: A sample and hold circuit uses an auto-zero feedback technique to cancel the DC level of the input signal and reference this signal to a new baseline. The circuit is based on an op-amp with two separate feedback loops. The first feedback loop is connected to the same op-amp input as the incoming signal and contains a capacitor to store charge from this signal during sample mode and set the output voltage during hold mode. The second feedback loop uses an auto-zero feedback technique and contains an integrator having a predetermined reference voltage, thereby allowing the DC level of the input signal to removed without the need for capacitors in the gain path of the circuit. This allows the sample and hold circuit to extract an embedded time varying signal from the input voltage. It can be configured for a high gain, high pass function, without the need for large electrolytic capacitors in the gain path, removing the problems associated with such capacitors.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: January 22, 2002
    Assignee: Zilog, Ind.
    Inventor: James W. Leith
  • Patent number: 6339368
    Abstract: A circuit for automatically driving a mechanical device at its resonance frequency is provided. To do so, the circuit detects non-resonance driving conditions of the mechanical device being coupled to and driven by such circuit. Based on such detection, the circuit generates a signal to drive the device at its resonance frequency.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: January 15, 2002
    Assignee: Zilog, Inc.
    Inventor: James W. Leith