Abstract: A towable conveyor for transporting and elevating articles and a method and system for towing a conveyor and conveying articles up inclines is provided. The conveyor system has an elevating carriage and a plurality of support elements for conveying articles up the conveyor. Specifically, the towable conveyor system comprises a conveyor having a support frame, a plurality of support elements, a drive end with a motor, and an idle end; an elevating carriage having a first end interconnected to the support frame of the conveyor, a second with two or more wheels, and a support member extending upwardly from the elevating carriage; a cable system for raising the conveyor into a position of use and for lowering the conveyor into a towing position; one or more locking mechanisms; and a hitch for connecting the conveyor to a rear end of a towing vehicle.

Abstract: An ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors each for providing two detection signals. The ESD protection circuit includes driver circuitry that produces trigger signals to clamp circuits that make conductive the clamp circuits in response to an ESD event based on the detection signals from the current mirrors.

Abstract: The present invention relates to a rule stop block. The rule stop block includes a block body and an adjustable slider. Exterior opposed end walls, opposed sidewalls, a top planar face and a bottom planar face define the block body. The adjustable slider is adjustably positioned within an interior of the block body and is adapted to engage a rule.

Abstract: An ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors each for providing two detection signals. The ESD protection circuit includes driver circuitry that produces trigger signals to clamp circuits that make conductive the clamp circuits in response to an ESD event based on the detection signals from the current mirrors.

Abstract: The present invention relates to a rule stop block. The rule stop block includes a block body and an adjustable slider. Exterior opposed end walls, opposed sidewalls, a top planar face and a bottom planar face define the block body. The adjustable slider is adjustably positioned within an interior of the block body and is adapted to engage a rule.

Abstract: An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

Abstract: An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

Abstract: An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

Abstract: An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

Abstract: Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

Abstract: An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.

Abstract: An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.

Abstract: Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

Abstract: The system and method permits the use of equipment that is located exterior to a container, such as a tank container liquid hydrocarbon material within which a sludge deposit has accumulated, and then inserted, as through an access opening in the side of the tank. In addition to other innovations, an improved hydraulic equipment positioning arrangement is provided, for both positioning, inserting and withdrawing the conduit structure and end effectors for accessing the sludge or sediment, which may include a leveling element preferably in the form of an hydraulic system that operates to move the assembly in a vertical plane as well as a rotary driven hydraulic system for driving the conduit structure along a long axis.

Abstract: A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.

Abstract: A platform assembly can be used in a motor vehicle, such as a truck, to support a person or objects. The platform assembly can have a frame with pivotal attachments to allow the frame to be at least partially collapsible. The platform can pivotally and removably attach to the frame.

Abstract: A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

Abstract: An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.

Abstract: A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.