Abstract: Memory and method for storing a plurality of memory bits. The memory has a data storage element and a processor. The data storage element has a plurality of lines, each having a plurality of segments having a plurality of data bits. A plurality of error correction codes are each associated with one of the lines. A plurality of validity bits, each being associated with one of the lines, are configured to indicate that one of the error correction codes associated with the one of the lines is valid or invalid. The processor is configured to generate one of the error correction codes for all of the data bits in the segments associated with one of the lines.

Abstract: Memory and method for storing a plurality of memory bits. The memory has a data storage element and a processor. The data storage element has a plurality of lines, each having a plurality of segments having a plurality of data bits. A plurality of error correction codes are each associated with one of the lines. A plurality of validity bits, each being associated with one of the lines, are configured to indicate that one of the error correction codes associated with the one of the lines is valid or invalid. The processor is configured to generate one of the error correction codes for all of the data bits in the segments associated with one of the lines.

Abstract: Memory and method for storing a plurality of memory bits. The memory has a data storage element and a processor. The data storage element has a plurality of lines, each having a plurality of segments having a plurality of data bits. A plurality of error correction codes are each associated with one of the lines. A plurality of validity bits, each being associated with one of the lines, are configured to indicate that one of the error correction codes associated with the one of the lines is valid or invalid. The processor is configured to generate one of the error correction codes for all of the data bits in the segments associated with one of the lines.

Abstract: Memory and method for storing a plurality of memory bits. The memory has a data storage element and a processor. The data storage element has a plurality of lines, each having a plurality of segments having a plurality of data bits. A plurality of error correction codes are each associated with one of the lines. A plurality of validity bits, each being associated with one of the lines, are configured to indicate that one of the error correction codes associated with the one of the lines is valid or invalid. The processor is configured to generate one of the error correction codes for all of the data bits in the segments associated with one of the lines.

Abstract: A low-power, compilable memory uses a charging pulse technique to improve access times over other low-power memory implementations. The memory includes circuitry configured to discharge a plurality of bit lines during an inactive memory access period to reduce power consumption. The memory also includes other circuitry that applies a charging pulse during an active memory access period on a select one of the plurality of bit lines in order to improve the memory access times. An automatic memory compiler adjusts a timing circuit to control the duration of the charging pulse and the enabling of a sense amplifier circuit during memory design. The memory compiler provides a programmable physical size of the memory and optimizes the access timing while ensuring reliable sensing. The compiler calculates timing for the timing circuit according to a mathematical formula that provides for highly accurate and predicable access time delays for multiple memory configurations.

Abstract: A compilier methodology including a stand alone memory interface which provides a user specified memory device of a required number of words of memory of a required bits per word. The stand alone memory interface is a tool to provide a menu showing multiple ways in which the user's request can be physically configured by varying the number of rows of memory, the number of blocks of memory, and the column multiplexing factor of the memory array. From this menu the user selects the memory configuration that best meets the user's requirements and is provided with either various models or representations (views) of the selected memory configuration or a GDS format data file. The views can be used to design large scale integrated circuits in which the memory device is embedded while the data file is used to generate photo mask for making the memory device as an integrated circuit.

Abstract: The occurrence of invalid data transitions on an output data bus (17) are reduced with an improved data sensing circuit (20). In a single block memory application, a self-controlled sense amplifier (21) eliminates the need for external timing control signals by triggering off the rail-to-rail voltage swings of a complementary bit line pair (BIT, BITB) of a memory array coupled to the inputs of the amplifier (21). Triggering off the bit lines (BIT, BITB) ensures that the amplifier (21) is not activated until valid data appears at its input, thereby preventing glitches on the output data bus (17) due to the amplifier (21) or associated latch (13). In a multiblock memory application, the data sensing circuit is further improved by eliminating invalid data transitions from appearing on the output data bus (17) through use of feedback.

Abstract: A configurable SRAM (21) is provided that is full diffused for increased speed and density and configurable for different word widths. Configuration signals are applied to control logic (28) for selecting a word width. The word width is smaller than or equal to a bit string of configurable SRAM (21). In a write operation, data input registers store and couple a word to a second bus. A shifter (27) receives the word from the second bus and shifts the bit locations of the word. A multiplexer (26) couples the shifted word to a first bus where write circuitry of read/write circuitry (24) writes the word to a selected bit string of a memory array (22) without affecting other bits of the selected bit string.In a read operation, a selected bit string is provided from the memory array (22) to read circuitry. The read circuitry provides the selected bit string to the first bus. The multiplexer (26) couples a word from the selected bit string to the shifter (27).

Abstract: A configurable decode circuit (11) having a plurality of inputs (12), a clock input (13), an output (14), and an output (16) is described. The configurable decode circuit (11) is a nor type decoder configurable to different address widths. A latch (17) stores the decode results. A bias circuit (29) enables the configurable decode circuit (11) starting a decode cycle. A differential input stage is coupled between the latch (17) and bias circuit (29). One side of the differential input stage comprises a plurality of transistors (23) coupled in parallel. Each control electrode of the plurality of transistors (23) is coupled to a respective input of inputs (12). The other side of the differential input stage comprises a transistor (28) coupled between the latch (17) and the bias circuit (29). A control electrode of the transistor (28) is coupled to common first electrodes of the plurality of transistors (23).

Abstract: A memory circuit uses sense amplifiers to amplify a low level differential data signal from the memory cells to full logic levels. A first sense amplifier converts the low level differential data signal to an intermediate differential voltage level at first and second nodes during the read cycle. A second sense amplifier converts the intermediate differential voltage level to the full logic level. The first and second sense amplifiers are powered down after sensing is complete. A circuit drives the intermediate differential data signal to an equilibrium voltage level when the sensing is complete to reduce the power up delay time of the second sense amplifier and thereby increase the operating speed of the memory circuit. A latching circuit is synchronized with the power down of the first sense amplifier to latch the output logic level at the end of the read cycle.

Abstract: A write priority detector in a multiport memory prioritizes write operations to memory cell by activating one of its enable signals to a memory cell upon receiving multiple address signals at different write ports of the multiport memory, each attempting to access the same memory cell. The other enable signals are de-activated. One prioritization scheme provides first-come first-serve access to the memory cell among completing address signals. Alternately, a fixed priority scheme always gives one enable signal first priority.