Abstract: A method of improving or modifying a fabricated circuit board having a circuit pattern of board traces etched thereon. First and second locations on the printed circuit board are identified for electrical connection of the two locations for the purpose of modifying the circuit board. A path is then selected from the first location to the second location generally without crossing of etched board traces. A metallic panel is provided and metal is removed from the panel to form a plurality of lay-flat traces in a configuration to match the selected path. Preferably, the lay-flat traces are plated with copper and then tin or solder. An overcoating of an insulating material, such as photo-imageable solder mask, is then applied. One of the lay-flat traces can then be removed from the panel and installed on the board to follow the selected path from the first location to the second location. Annular pads at the opposed ends of the lay-flat trace are soldered to the two locations.