Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler component is extended to accommodate a number of dual decor commands which invoke host system facilities to execute terminal based commands either synchronously or asynchronously through the automatic creation of host shell mechanisms directly accessible by emulated system users. The server facilities include a network terminal driver (NTD) server for executing emulated system user terminal requests through host system drivers.

Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a network terminal driver (NTD) component operating in the host memory. Configuration command means are provided for initially configuring a host terminal to operate in a plurality of asynchronous driver (ATD) modes implemented by the NTD component. When a terminal has been configured by a user to run applications written for the ATD driver, it sets a mode indication which causes the NTD component to respond to user applications as an ATD driver and determine if each ATD request can be carried out with functionality included within the NTD component.

Abstract: A controller for controlling a large number of terminals and workstations semantically interprets entering character sequences with little load on its computing power by means of dispatching under the control of a hierarchical arrangement of lookup tables, wherein one possible action that may be dispatched to is the selection of another table in the hierarchy. Characters may thus be interpreted in the context of the characters that have preceded them. Another possible action is to switch to a memory search mode of interpretation, eliminating the need to provide lookup tables for infrequently occurring sequences.

Abstract: In a data processing system having a plurality of remote terminals, possibly of several kinds, connected by a plurality of communications media, also possibly of several kinds, from which terminals users may run a plurality of application programs in the central processing unit (CPU) of the data processing system, the CPU is provided with a network terminal driver for regulating transmissions between the various application programs and the various types of terminals over the various types of communications media. Means are provided for specifying the characteristics of the various types of application programs, terminals, and communications media, and the network terminal drive is responsive to those means.

Abstract: A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer system is such that one of the processors is allocated the bulk of memory band-width with the other processor taking the remainder. Arbitration for memory allocation is accomplished via a combination of a new firmware instruction and a semaphore.

Abstract: A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller.

Abstract: A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.