Abstract: Incoming diphase signals E which have base bit intervals delineated by spaced clocking signals with data information occurring between the clocking signals are fed to a four bit shift register 10 which in cooperation with an exclusive OR-gate 14 generates a pulse D for each diphase signal E transition. Upon receipt of a preamble comprising four diphase signal transitions, a shift register 16 provides a signal MSR which initiates the decoding of the following data information. A counter 24 stores counts related to the time intervals between each two successive clocking signals and counters 26 and 28 store a count related to an immediately subsequent time period which is three-fourths of the time interval. The occurrence of data information is sensed by a logic array 20 during successive time periods and a non-return to zero mark-space output signal K is stored in a flip-flop 22. The logic array 20 continually updates the counts stored by the counters 24, 26-28.

Abstract: A circuit for detecting the relative time of occurrence of first and second signals applied to first and second terminals includes a pair of bistable flip-flops. In response to the occurrence first of the first signal the first one of the flips-flops is set to initiate the generation of a control signal. A time delay responds to the control signal and upon expiration of the time delay interval the second one of the flip-flops is set and this in turn resets the first flip-flop to terminate the control signal. In response to the first occurrence first of the second signal the second one of the flip-flops is set and this inhibits the setting of the first flip-flop. In the event that the first and second signals occur simultaneously the second flip-flop sets quickly resetting the first flip-flop. In response to either signal, a conductive path is established between the terminals.