Abstract: A dummy wordline in a semiconductor memory controls the timing of the firing of sense amplifiers in the memory in relation to the firing of active wordlines in the memory. The dummy wordline receives a timing signal at the same time that an active wordline is fired, and the length of the dummy wordline is set during fabrication so the timing signal propagating along the dummy wordline arrives at the sense amplifiers and fires the sense amplifiers at a desired time.

Abstract: Bit line load circuitry that eliminates wasted standby current flowing to an unused (i.e., repaired-out) column in a Static Random Access Memory (SRAM) device includes a fuse or an anti-fuse interposed between one or more PMOS bit line load devices in the unused column and the supply voltage. Blowing the fuse or anti-fuse isolates the bit line load devices from the supply voltage so the devices draw no current, thus reducing the total standby current of the SRAM device. The fuse may be blown with a laser or with excessive current, and the anti-fuse may be blown with excessive voltage.

Abstract: A dummy wordline in a semiconductor memory controls the timing of the firing of sense amplifiers in the memory in relation to the firing of active wordlines in the memory. The dummy wordline receives a timing signal at the same time that an active wordline is fired, and the length of the dummy wordline is set during fabrication so the timing signal propagating along the dummy wordline arrives at the sense amplifiers and fires the sense amplifiers at a desired time.

Abstract: Bit line load circuitry that eliminates wasted standby current flowing to an unused (i.e., repaired-out) column in a Static Random Access Memory (SRAM) device includes a fuse or an anti-fuse interposed between one or more PMOS bit line load devices in the unused column and the supply voltage. Blowing the fuse or anti-fuse isolates the bit line load devices from the supply voltage so the devices draw no current, thus reducing the total standby current of the SRAM device. The fuse may be blown with a laser or with excessive current, and the anti-fuse may be blown with excessive voltage.

Abstract: A dummy wordline in a semiconductor memory controls the timing of the firing of sense amplifiers in the memory in relation to the firing of active wordlines in the memory. The dummy wordline receives a timing signal at the same time that an active wordline is fired, and the length of the dummy wordline is set during fabrication so the timing signal propagating along the dummy wordline arrives at the sense amplifiers and fires the sense amplifiers at a desired time.

Abstract: Bit line load circuitry that eliminates wasted standby current flowing to an unused (i.e., repaired-out) column in a Static Random Access Memory (SRAM) device includes a fuse or an anti-fuse interposed between one or more PMOS bit line load devices in the unused column and the supply voltage. Blowing the fuse or anti-fuse isolates the bit line load devices from the supply voltage so the devices draw no current, thus reducing the total standby current of the SRAM device. The fuse may be blown with a laser or with excessive current, and the anti-fuse may be blown with excessive voltage.

Abstract: An inventive sense amplifier in a memory device includes a feedback-controlled differential amplifier with a pair of differential output terminals, one of which is driven to ground and the other of which is driven to the supply voltage VCC when a logic “1” or “0” bit is sensed by the sense amplifier. Pre-charge circuitry pre-charges the output terminals of the differential amplifier to the supply voltage VCC before a logic bit is sensed so little or no time is wasted pulling one of the terminals up to the supply voltage VCC when a logic bit is sensed. Tri-state output circuitry connected to the differential amplifier outputs a sensed logic bit to an internal data bus of the memory device, and the tri-state nature of the output circuitry allows the circuitry to present a high impedance to the internal data bus. As a result, the sense amplifier can share the internal data bus with other sense amplifiers without interfering with the operation of the other sense amplifiers.

Abstract: A synchronous memory device includes separate pulse generators to produce write recovery pulses locally for input to each local column selector. The local generation of the write recovery pulse eliminates a write recovery line extending from the control logic to each of the local write drivers thereby simplifying control of timing within the device. The local pulse generators provide pulses of the write recovery signal in response to the transition of a write data signal from the true to the not-true state.