Patents by Inventor James Walter Blatchford
James Walter Blatchford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8607170Abstract: A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration.Type: GrantFiled: March 1, 2012Date of Patent: December 10, 2013Assignee: Texas Instruments IncorporatedInventor: James Walter Blatchford
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Publication number: 20130316505Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.Type: ApplicationFiled: July 26, 2013Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventors: James Walter BLATCHFORD, JR., Yong Seok CHOI
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Patent number: 8584053Abstract: A method for designing a mask set including at least one mask includes the implementation of at least one design rule from a set of design rules. The design rules include rules relating to allowable spacing between adjacent features, overlap of features defined by different masks in the mask set, and other characteristics of the mask set.Type: GrantFiled: June 22, 2011Date of Patent: November 12, 2013Assignee: Texas Intruments IncorporatedInventor: James Walter Blatchford
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Patent number: 8580675Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.Type: GrantFiled: March 1, 2012Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventors: James Walter Blatchford, Scott William Jessen
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Patent number: 8575020Abstract: An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.Type: GrantFiled: March 1, 2012Date of Patent: November 5, 2013Assignee: Texas Instruments IncorporatedInventor: James Walter Blatchford
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Patent number: 8569838Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.Type: GrantFiled: March 16, 2011Date of Patent: October 29, 2013Assignee: Texas Instruments IncorporatedInventors: James Walter Blatchford, Jr., Yong Seok Choi
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Publication number: 20130244144Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Texas Instruments IncorporatedInventors: James Walter BLATCHFORD, Yong Seok CHOI, Thomas J. ATON
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Publication number: 20130246983Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Texas Instruments IncorporatedInventors: James Walter BLATCHFORD, Yong Seok CHOI, Thomas J. ATON
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Patent number: 8513105Abstract: An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.Type: GrantFiled: October 14, 2010Date of Patent: August 20, 2013Assignee: Texas Instruments IncorporatedInventors: Gregory Charles Baldwin, James Walter Blatchford
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Patent number: 8461038Abstract: An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.Type: GrantFiled: March 1, 2012Date of Patent: June 11, 2013Assignee: Texas Instruments IncorporatedInventor: James Walter Blatchford
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Patent number: 8455180Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8W1 to 1.3W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.Type: GrantFiled: October 29, 2010Date of Patent: June 4, 2013Assignee: Texas Instruments IncorporatedInventors: James Walter Blatchford, Yong Seok Choi, Thomas J. Aton
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Publication number: 20130069244Abstract: A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.Type: ApplicationFiled: June 21, 2012Publication date: March 21, 2013Applicant: Texas Instruments IncorporatedInventor: James Walter Blatchford
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Patent number: 8372743Abstract: An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.Type: GrantFiled: March 1, 2012Date of Patent: February 12, 2013Assignee: Texas Instruments IncorporatedInventor: James Walter Blatchford
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Publication number: 20120331425Abstract: A method for designing a mask set including at least one mask includes the implementation of at least one design rule from a set of design rules. The design rules include rules relating to allowable spacing between adjacent features, overlap of features defined by different masks in the mask set, and other characteristics of the mask set.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Inventor: James Walter Blatchford
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Patent number: 8304317Abstract: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.Type: GrantFiled: December 29, 2009Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Yiming Gu, James Walter Blatchford
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Publication number: 20120235242Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.Type: ApplicationFiled: March 16, 2011Publication date: September 20, 2012Applicant: Texas Instruments IncorporatedInventors: James Walter Blatchford, JR., Yong Seok Choi
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Publication number: 20120225552Abstract: An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.Type: ApplicationFiled: March 1, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: James Walter Blatchford
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Publication number: 20120225551Abstract: An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.Type: ApplicationFiled: March 1, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: James Walter Blatchford
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Publication number: 20120223439Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.Type: ApplicationFiled: March 1, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Walter Blatchford, Scott William Jessen
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Publication number: 20120225550Abstract: An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.Type: ApplicationFiled: March 1, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: James Walter Blatchford