Abstract: Described is an isolated somatic stem cell that is 2 to less than 6 micrometer in size and Lgr5+. Methods of preparing and using the cell are also described.

Abstract: Techniques and structures relating to virtual graphics processing units (VGPUs) are disclosed. A VGPU may appear to software as an independent hardware GPU. However, two or more VGPUs can be implemented on the same GPU through the use of control structures and by duplicating some (but not all) hardware elements of the GPU. For example, additional registers and storage space may be added in a GPU supporting multiple VGPUs. Different execution priorities may be set for tasks and threads that correspond to the different supported VGPUs. Memory address space for the VGPUs may also be managed, including use of virtual address space for different VGPUs. Halting and resuming execution of different VGPUs allows for fine-grained execution control in various embodiments.

Abstract: A method of evaluating an action includes (1) obtaining a first stem-cell data related to a subject before performing the action, (2) performing the action on the subject, (3) obtaining a second stem-cell data related to the subject after performing the action, and (4) identifying the effect of the action on the subject based on the first stem-cell data and the second stem-cell data. The subject may be a human or an animal. The action may be taking a drug or taking a nutrient or dietary supplement, which may include fucoidan. Each of the first and second stem-cell data may include the count of a type or types of stem cells and/or the percentage of the type or types of stem cells and may be obtained by the same method including counting cells using a cell counter or cell counting device such as flow cytometer.

Abstract: An apparatus substantially updates all the phase shifter values of a phased array antenna by using “global write” to update these parameters to all phased-array transformation circuits simultaneously via a serial bus. Antenna elements, each controlled by a phased-array transformation circuit, are individually configured to transform phase and gain according to a register array. The register array has a local register group and a central register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a central register controlling overall beam steering function. The apparatus is configured to efficiently elaborate phase shift weights into a submodule of a phase array antenna system with low noise and bandwidth.

Abstract: A somatic stem cell that is CD10+, CXCR4+, and CD31+ and another somatic stem cell that is CD105+, CD44+, and nestin+. Also disclosed are both a method of preparing these stem cells and a method of using them to treat degenerative diseases, e.g., a muscle-degenerative disease. The invention further includes making and using liver cells derived from the somatic cell that is CD105+, CD44+, and nestin+.

Abstract: Disclosed are methods of using blastomere-like stem cells to decrease a level of myeloid-derived suppressor cells (MDSCs). A method for decreasing a level of myeloid-derived suppressor cells (MDSCs) in a human subject, including: injectionally, orally or transdermally administering to the human subject an amount of human blastomere-like stem cells, autologous to the human subject, at 1×108 to 1×1011 cells each time once every two weeks, for example.

Abstract: A 5-wire touch screen system includes a touch screen (10) including a wiper (11) and a resistive layer (16) aligned with the wiper and first (UL), second (UR), third (LR), and fourth (LL) resistive layer contacts, wherein a touch on the screen presses a small portion of the wiper against the resistive layer, producing a touch resistance (RZ) between them at a touch point on the resistive layer. The wiper and various contacts are selectively coupled to first (VDD) and second (GND) reference voltages, respectively, to generate an analog touch voltage (VZ) at the touch point. The wiper and various contacts are selectively coupled to an analog input (56) and a reference voltage input of an ADC (48) for converting the touch voltage (VZ) to a digital representation. Analog voltages (VX) and (VY) at the touch point are converted to corresponding digital representations by the ADC.

Abstract: An anti-torque rotor of a helicopter, having: a supporting body; a drive shaft which rotates about a first axis with respect to the supporting body; a hub connected operatively to drive shaft and angularly fixed with respect to first axis; at least one blade which is connected operatively to hub, is angularly fixed with respect to first axis, and is angularly movable with respect to a second axis to adjust the pitch angle of blade; and an actuator which can be operated to rotate blade about second axis to adjust the pitch angle of blade; actuator has an electric motor which generates torque along the first axis; and a mechanical stage interposed between the electric motor and blade, and designed to convert the torque into rotation of blade about the respective second axes; electric motor is fixed to supporting body.

Abstract: A method and apparatus for saving power in integrated circuits is disclosed. An IC includes functional circuit blocks which are not placed into a sleep mode when idle. A power management circuit may monitor the activity levels of the functional circuit blocks not placed into a sleep mode. When the power management circuit detects that an activity level of one of the non-sleep functional circuit blocks is less than a predefined threshold, it reduce the frequency of a clock signal provided thereto by scheduling only one pulse of a clock signal for every N pulses of the full frequency clock signal. The remaining N?1 pulses of the clock signal may be inhibited. If a high priority transaction inbound for the functional circuit block is detected, an inserted pulse of the clock signal may be provided to the functional unit irrespective of when a most recent regular pulse was provided.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: Techniques and structures relating to virtual graphics processing units (VGPUs) are disclosed. A VGPU may appear to software as an independent hardware GPU. However, two or more VGPUs can be implemented on the same GPU through the use of control structures and by duplicating some (but not all) hardware elements of the GPU. For example, additional registers and storage space may be added in a GPU supporting multiple VGPUs. Different execution priorities may be set for tasks and threads that correspond to the different supported VGPUs. Memory address space for the VGPUs may also be managed, including use of virtual address space for different VGPUs. Halting and resuming execution of different VGPUs allows for fine-grained execution control in various embodiments.

Abstract: Provided are 6-5 membered fused pyridine ring compounds according to Formula (I) or pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising these compounds and their use in therapy. In particular, provided is the use of 6-5 membered fused pyridine ring compounds in the treatment of Bruton's Tyrosine Kinase (Btk) mediated disorders.

Abstract: Compositions and methods for detecting Trichomonas vaginalis are provided.

Abstract: A personal cloud contained in a case for a portable computing device such as a tablet personal computer (PC), mobile phones, portable media players, or the like. The personal cloud case may be fitted with memory, a network connection, two-way wireless charging, external memory slots, external connections and other components for portable personal cloud computing.

Abstract: The present invention relates to a photocurable adhesive composition and the use of the same. Specifically, said photocurable adhesive composition mainly comprises, based on 100 parts by weight of the adhesive composition, component A: from 70 to 99 parts by weight of one or more polymers carrying (meth)acryloxyl group; component B: from 0 to 30 parts by weight, preferably from 0 to 25 parts by weight of one or more (meth)acrylates monomers; component C: from 0.5 to 10 parts by weight of at least one UV absorber; and component D: from 0 to 5 parts by weight of antioxidant. The present invention also relates to the use of the adhesive composition mentioned above in the production of an ITO substrate for temporarily bonding a substrate and a temporary carrier and going through a high temperature processing, for example, at a temperature of ?160° C., preferably, from 160° C. to 260° C., more preferably from 240° C. to 250° C.

Abstract: A multimode multiband wireless device includes a broadband RF power amplifier that receives RF signals and produces amplified RF signals in a cellular band in a broadband, and a coexist filter coupled to the input of the broadband RF power amplifier. The coexist filter can reject RF noise in a predetermined frequency range in the broadband adjacent to the cellular band.

Abstract: A 5-wire touch screen system includes a touch screen (10) including a wiper (11) and a resistive layer (16) aligned with the wiper and first (UL), second (UR), third (LR), and fourth (LL) resistive layer contacts, wherein a touch on the screen presses a small portion of the wiper against the resistive layer, producing a touch resistance (RZ) between them at a touch point on the resistive layer. The wiper and various contacts are selectively coupled to first (VDD) and second (GND) reference voltages, respectively, to generate an analog touch voltage (VZ) at the touch point. The wiper and various contacts are selectively coupled to an analog input (56) and a reference voltage input of an ADC (48) for converting the touch voltage (VZ) to a digital representation. Analog voltages (VX) and (VY) at the touch point are converted to corresponding digital representations by the ADC.

Abstract: Techniques are disclosed relating to handling page faults created by a processor unit. In some embodiments, such techniques may be used within the context of graphics processor units (GPUs) to reduce the chances that a page fault will result in a GPU-pipeline stall. In one embodiment, a processor includes a graphics processor pipeline and a memory management unit. The graphics processor pipeline includes a plurality of pipeline stages. The memory management unit is configured to determine that a first data request from a first of the plurality of pipeline stages causes a page fault, and to service requests from one or more others of the plurality of pipeline stages while the page fault is being serviced.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.