Patents by Inventor James Warnock
James Warnock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8104014Abstract: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.Type: GrantFiled: January 30, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Ruchir Puri, Haifeng Qian, Chin Ngai Sze, James Warnock
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Patent number: 7643981Abstract: The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.Type: GrantFiled: July 22, 2004Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Sang Y. Lee, Vasant B. Rao, Jeffrey Soreff, James Warnock, David Winston
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Publication number: 20090193377Abstract: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventors: Ruchir Puri, Haifeng Qian, Chin Ngai Sze, James Warnock
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Patent number: 7340682Abstract: An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system display surface. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications.Type: GrantFiled: May 9, 2003Date of Patent: March 4, 2008Assignee: xSides CorporationInventors: D. David Nason, J. Scott Campbell, Phillip Brooks, Carson Kaan, Thomas C. O'Rourke, James Warnock, John Easton
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Publication number: 20070061647Abstract: An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.Type: ApplicationFiled: October 25, 2006Publication date: March 15, 2007Inventors: Sang Dhong, Joel Silberman, Osamu Takahashi, James Warnock, Dieter Wendel
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Publication number: 20060242506Abstract: This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system clock. This enhancement improves the frequency at which the test clocks switch and improve the testing throughput by reducing testing time, resulting in significant reductions in testing hardware and overall time required for system test, without compromising any of the benefits associated with conventional LSSD techniques. The method further enhances the distribution of the test clock signals to points throughout the entire chip, with a distribution network that is tailored according to a desired LBIST speed.Type: ApplicationFiled: April 25, 2005Publication date: October 26, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Warnock, William Huott
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Publication number: 20060095802Abstract: An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.Type: ApplicationFiled: October 28, 2004Publication date: May 4, 2006Applicant: International Business Machines CorporationInventors: Sang Dhong, Joel Silberman, Osamu Takahashi, James Warnock, Dieter Wendel
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Method of timing model abstraction for circuits containing simultaneously switching internal signals
Publication number: 20060031797Abstract: The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assuming maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculating the actual interference between the signals.Type: ApplicationFiled: July 22, 2004Publication date: February 9, 2006Applicant: International Business Machines CorporationInventors: Jeffrey Soreff, James Warnock -
Publication number: 20060020443Abstract: The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.Type: ApplicationFiled: July 22, 2004Publication date: January 26, 2006Applicant: International Business Machines CorporationInventors: Sang Lee, Vasant Rao, Jeffrey Soreff, James Warnock, David Winston
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Publication number: 20050242439Abstract: A structure (and method) for an electronic chip, includes a first circuit design module having a first grid and a second circuit design module having a second grid. The first grid and the second grid are interconnected in a fabrication layer no later than a first metallization layer that accumulates a charge during a plasma process in the fabrication.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenneth DeVries, Jeffrey Gambino, Stephen Luce, James Warnock, Francis White
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Publication number: 20050071790Abstract: In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.Type: ApplicationFiled: September 26, 2003Publication date: March 31, 2005Inventors: Erwin Behnen, Jeffrey Soreff, James Warnock, Dieter Wendel
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Publication number: 20050071794Abstract: In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.Type: ApplicationFiled: October 8, 2004Publication date: March 31, 2005Inventors: Erwin Behnen, Jeffrey Soreff, James Warnock, Dieter Wendel
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Publication number: 20040032423Abstract: An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system display surface. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications.Type: ApplicationFiled: May 9, 2003Publication date: February 19, 2004Applicant: xSides CorporationInventors: D. David Nason, J. Scott Campbell, Phillip Brooks, Carson Kaan, Thomas C. O'Rourke, James Warnock, John Easton
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Publication number: 20040027387Abstract: An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system display surface. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications.Type: ApplicationFiled: May 9, 2003Publication date: February 12, 2004Applicant: xSides CorporationInventors: D. David Nason, J. Scott Campbell, Phillip Brooks, Carson Kaan, Thomas C. O'Rourke, James Warnock, John Easton
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Patent number: 6630943Abstract: An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system display surface. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications.Type: GrantFiled: September 20, 2000Date of Patent: October 7, 2003Assignee: xSides CorporationInventors: D. David Nason, J. Scott Campbell, Phillip Brooks, Carson Kaan, Thomas C. O'Rourke, James Warnock, John Easton