Patents by Inventor James Warren Wilson
James Warren Wilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6989297Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10–17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on-opposite sides of a substrate.Type: GrantFiled: August 25, 2004Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Robert David Sebesta, James Warren Wilson
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Patent number: 6919514Abstract: Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.Type: GrantFiled: September 15, 2003Date of Patent: July 19, 2005Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
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Patent number: 6900545Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.Type: GrantFiled: March 16, 2000Date of Patent: May 31, 2005Assignee: International Business Machines CorporationInventors: Robert David Sebesta, James Warren Wilson
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Patent number: 6739048Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: GrantFiled: January 27, 2000Date of Patent: May 25, 2004Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Patent number: 6730857Abstract: Embedded flush circuitry features are fabricated by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a later of dielectric material.Type: GrantFiled: March 13, 2001Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
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Publication number: 20040064939Abstract: Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.Type: ApplicationFiled: September 15, 2003Publication date: April 8, 2004Applicant: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
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Patent number: 6455139Abstract: Printed circuit boards, cards and chip carriers are fabricated by treating an already circuitized substrate with a swelling agent, then treating the circuitized substrate with a composition containing an alkaline permanganate, a chromate and/or chlorite and then applying a metal layer to coat the circuitized portion of the substrate.Type: GrantFiled: July 31, 2001Date of Patent: September 24, 2002Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Konstantinos I. Papathomas, Timothy Leroy Wells, James Warren Wilson
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Publication number: 20020129972Abstract: Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.Type: ApplicationFiled: March 13, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
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Publication number: 20020078562Abstract: A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: ApplicationFiled: January 27, 2000Publication date: June 27, 2002Inventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Publication number: 20010040047Abstract: Printed circuit boards, cards and chip carriers are fabricated by treating an already circuitized substrate with a swelling agent, then treating the circuitized substrate with a composition containing an alkaline permanganate, a chromate and/or chlorite and then applying a metal layer to coat the circuitized portion of the substrate.Type: ApplicationFiled: July 31, 2001Publication date: November 15, 2001Inventors: John Joseph Konrad, Konstantinos I. Papathomas, Timothy Leroy Wells, James Warren Wilson
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Patent number: 6296897Abstract: Printed circuit boards, cards and chip carriers are fabricated by treating an already circuitized substrate with a swelling agent, then treating the circuitized substrate with a composition containing an alkaline permanganate, a chromate and/or chlorite and then applying a metal layer to coat the circuitized portion of the substrate.Type: GrantFiled: August 12, 1998Date of Patent: October 2, 2001Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Konstantinos I. Papathomas, Timothy Leroy Wells, James Warren Wilson
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Patent number: 6259037Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.Type: GrantFiled: October 4, 1999Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Natalie Barbara Feilchenfeld, John Steven Kresge, Scott Preston Moore, Ronald Peter Nowak, James Warren Wilson
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Patent number: 6150716Abstract: A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate including first and second opposed faces. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. In any case, the IC chip is electrically connected to the chip mounting pads either by the solder ball or wire bond connections.Type: GrantFiled: January 15, 1997Date of Patent: November 21, 2000Assignee: International Business Machines CorporationInventors: Stephen Wesley MacQuarrie, Wayne Russell Storr, James Warren Wilson
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Patent number: 6131279Abstract: A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: GrantFiled: January 8, 1998Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Patent number: 6077766Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel--gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.Type: GrantFiled: June 25, 1999Date of Patent: June 20, 2000Assignee: International Business Machines CorporationInventors: Robert David Sebesta, James Warren Wilson
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Patent number: 6027858Abstract: A process of tenting plated through holes with a photoimageable dielectric is provided which includes a dielectric film comprising a photoimageable epoxy based resin layer and a peelable polyester layer. In accordance with the process of the present invention, the peelable polyester layer of the dielectric film is removed prior to baking, developing, patterning or curing the structure.Type: GrantFiled: June 6, 1997Date of Patent: February 22, 2000Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, Heinke Marcello, James Warren Wilson, William Earl Wilson
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Patent number: 6013417Abstract: Circuitry is formed on a substrate having at least one plated through-hole employing two different photoresist materials. A first photoresist is applied on a conductive layer located on a substrate and is developed to define a desired conductive circuit pattern. A second photoresist is laminated onto the structure and is developed so that the second photoresist material remains in the vicinity of the through-hole. The conductive layer is etched to provide the desired circuit pattern, and the remaining portions of the second and first photoresists are removed.Type: GrantFiled: April 2, 1998Date of Patent: January 11, 2000Assignee: International Business Machines CorporationInventors: Robert David Sebesta, James Warren Wilson
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Patent number: 6006428Abstract: The present invention provides an organic chip carrier particularly useful with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.Type: GrantFiled: April 1, 1998Date of Patent: December 28, 1999Assignee: International Business Machines CorporationInventors: Natalie Barbara Feilchenfeld, John Steven Kresge, Scott Preston Moore, Ronald Peter Nowak, James Warren Wilson
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Patent number: 5966803Abstract: An electronic device package in the form of a ball grid array package is formed adding a single layer of conductive material including circuitry having trace lines, wire bond pads, and solder ball pads electrically coupled together. Thin film circuitization techniques are used on a polyimide laminate substrate to accommodate greater than 100 input/output contacts of an electronic device on a single layer. Thus, the package will not have vias or other conductive type through holes as in multiple conductive layer ball grid array packages.Type: GrantFiled: May 12, 1997Date of Patent: October 19, 1999Assignee: International Business Machines CorporationInventor: James Warren Wilson
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Patent number: 5939783Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.Type: GrantFiled: May 5, 1998Date of Patent: August 17, 1999Assignee: International Business Machines CorporationInventors: Eric Herman Laine, James Warren Wilson