Abstract: There is provided a fan assembly comprising a motor-driven impeller arranged to generate an airflow, an air outlet arranged to emit the airflow, a plurality of sensors arranged to measure a value for each of a plurality of air quality characteristics, a display and a processor. The processor is configured to receive measured values for each of the plurality of air quality characteristics, identify one of a corresponding set of intervals within which the measured value falls and select an air quality index value associated with the identified interval. The processor is then configured to identify the highest of the selected air quality index values as a current overall air quality index value and to cause the display to display a time series plot of the current air quality index value and a number of preceding air quality index values.

Abstract: Interconnect systems and method of operating such are disclosed. A plurality of nodes coupled via a packet transport path form an interconnect and the nodes provide ingress points to the interconnect for a plurality of packet sources. A central controller holds permitted rate indications for each of the plurality of packet sources, in accordance with which each packet source sends packets via the interconnect. The nodes each respond to packet collision event at that node by sending a collision report to the central controller. In response the central controller, in respect of a collision pair of packet sources associated with the packet collision, decreases the permitted rate indication corresponding to a packet source of the collision pair of packet sources which currently has the higher permitted rate indication. Periodically the permitted rate indications of all of the packet sources are increased, subject to a maximum permitted rate indication for each.

Abstract: An apparatus and method for operating a ring interconnect are disclosed. The ring interconnect has a plurality of nodes that are used to connect to associated components, and is arranged to transport a plurality of slots around the ring interconnect between the nodes in order to transfer items of traffic allocated into those slots between components connected to the nodes. For each item of traffic, one of the components acts as a source to allocate that item of traffic into a slot, and another components acts as destination to seek to remove that item of traffic from the slot. In a default mode of operation, the ring interconnect is arranged to allow all of the slots to be available for transfer of any items of traffic.

Abstract: A ring interconnect system comprises a plurality of nodes. Each node is connected to two other nodes to form a ring interconnect. Every pair of nodes is connected by an inter-node path for that pair of nodes distinct from the ring interconnect. Each of the nodes comprises a message buffer to buffer messages received from at least one device associated with the node. Each of the nodes also comprises activity level circuitry to transmit an activity indication, when a number of the messages in the message buffer is equal to or above a threshold, to each other node of the plurality of nodes via the respective inter-node paths. Each of the nodes also comprises arbitrator circuitry to receive the activity indications from each other node and from the activity level circuitry, and to allow ingress of a message from the message buffer onto the ring interconnect in dependence on the activity indications. Also provided is a method of operating a node of a ring interconnect system.

Abstract: An apparatus and method for operating a ring interconnect are disclosed. The ring interconnect has a plurality of nodes that are used to connect to associated components, and is arranged to transport a plurality of slots around the ring interconnect between the nodes in order to transfer items of traffic allocated into those slots between components connected to the nodes. For each item of traffic, one of the components acts as a source to allocate that item of traffic into a slot, and another components acts as destination to seek to remove that item of traffic from the slot. In a default mode of operation, the ring interconnect is arranged to allow all of the slots to be available for transfer of any items of traffic.

Abstract: An apparatus (300) for processing data comprises a plurality of memory access request sources (102,104) which generate memory access requests. Each of the memory access request sources has a local memory (106,108), and the apparatus also includes a shared memory (110). When the memory access requests are atomic memory access requests, contention may arise over common data. When this occurs, the present technique triggers a switch of processing data in the local memory of a memory access request source to processing data in the shared memory.

Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

Abstract: There is provided an apparatus comprising power state determination circuitry to determine a power state of a processing circuit; and control circuitry to issue a control signal relating to an item of data stored in a first storage circuitry. When the power state of the processing circuit is a predetermined state, the control circuitry issues a further control signal to a second storage circuitry to indicate whether the item of data is to be retained by the second storage circuitry.

Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

Abstract: An apparatus and method are provided for managing a cache. The cache is arranged to comprise a plurality of cache sections, where each cache section is powered independently of the other cache sections in the plurality of cache sections, and the apparatus has power control circuitry to control power to each of the cache sections. The power control circuitry is responsive to a trigger condition indicative of an ability to operate the cache in a power saving mode, to perform a latency evaluation process to determine a latency indication for each of the cache sections, and to control which of a subset of the cache sections to power off in dependence on the latency indication. This can allow the power consumption savings realised by turning off one or more cache sections to be optimised to take into account the current system state.

Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

Abstract: An apparatus for handling resets corresponding to multiple reset domains comprises a transport network interconnecting elements to enable data to be transferred from one element to another, ingress circuitry to couple elements to the transport network, and egress circuitry to couple the transport network to the elements. The ingress circuitry couples source elements to the transport network, and is responsive to receiving data from a source element to generate at least one transport packet in order to send that data over the transport network. Each transport packet comprises a reset domain indicator indicative of the reset domain in which the source element operates. The egress circuitry couples the transport network to destination elements and, whilst a reset of a particular reset domain is asserted, discards transport packets for which the reset domain indicator indicates the particular reset domain.

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

Abstract: Aspects of the present disclosure relate to an interconnect comprising an interface to couple to a master device, the interface comprising buffer storage. The interface is configured to receive a request from the master device for data comprising a plurality of data blocks, the master device requiring the data blocks in a defined order. A data collator is configured to: receive the request; issue a data pull request to cause the interface to allocate buffer space in the buffer storage for buffering the requested data; and responsive to receiving a confirmation that the buffer space is allocated, provide the requested data to the buffer storage. The interface is configured to employ the buffer storage to enable re-ordering of the plurality of data blocks of the requested data, prior to outputting the plurality of data blocks to the master device; and output the plurality of data blocks to the master device in the defined order.