Abstract: A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices.

Abstract: A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices.

Abstract: A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar.

Abstract: A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar.

Abstract: An amplifier system is provided for amplifying an input signal to provide an amplified output signal, amplifying an amplified input signal to provide a further amplified output signal, and phase delay compensating variations of the amplifications of the amplified output signal and the further amplified output signal for providing the further amplified output signal with substantially linear amplification under a variable load.

Abstract: A bipolar transistor amplifier with improved base biasing is disclosed. In the bias circuit of the present invention, the bias current only varies with the log(log) of variations in .beta. of the NPN transistors, making the circuit particularly resistant to temperature and process induced variations in .beta.. A feedback loop also insures that the bias current will remain constant under normal operating conditions. In several embodiments of the present invention, the bias signal and the input signal are kept separate, reducing interference. The amplifier and bias circuit provides a large amount of voltage headroom even with low supply voltages.