Abstract: Systems and methods relate to a bus adapter for a storage network. The bus adaptor includes a context memory comprising a first storage for uncacheable exchange resource indicators (XRI) and a second storage for cacheable XRI. The bus adapter also includes a host backing store unit configured to provide access to the different tier memories present locally or externally in the host memory extension using several caching sub-units and with the capability of an optional pinning operation for the cacheable XRI based upon at least one of input/output phase, first in line up to a limit, a region of a virtual context address associated with the cacheable XRI indicators, a protocol associated with the cacheable XRI, a size of a transaction, or work queue information.

Abstract: Systems and methods of communicating in a network use rate limiting. Rate limiting units (either receive side or transmit side) can perform rate limiting in response to a) a maximum number of bytes that can be solicited over a first period of time is exceeded, b) a maximum number of bytes that are outstanding over a second period of time is exceeded; or c) a maximum number of commands that are outstanding over a period of time is exceeded as part of CMD_RXRL. The CMD_RXRL can have three components (a) max bytes, b) outstanding bytes, c) outstanding commands. TXRL contains the component of max bytes or maximum number of bytes that can be transmitted over a third period of time to match the speed of a receive link, or any node or link through the network/fabric.

Abstract: Systems and methods of communicating in a network use rate limiting. Rate limiting units (either receive side or transmit side) can perform rate limiting in response to a) a maximum number of bytes that can be solicited over a first period of time is exceeded, b) a maximum number of bytes that are outstanding over a second period of time is exceeded; or c) a maximum number of commands that are outstanding over a period of time is exceeded as part of CMD_RXRL. The CMD_RXRL, can have three components (a) max bytes, b) outstanding bytes, c) outstanding commands. TXRL, contains the component of max bytes or maximum number of bytes that can be transmitted over a third period of time to match the speed of a receive link, or any node or link through the network/fabric.

Abstract: Systems and methods relate to a bus adapter for a storage network. The bus adaptor includes a context memory comprising a first storage for uncacheable exchange resource indicators (XRI) and a second storage for cacheable XRI. The bus adapter also includes a host backing store unit configured to provide access to the different tier memories present locally or externally in the host memory extension using several caching sub-units and with the capability of an optional pinning operation for the cacheable XRI based upon at least one of input/output phase, first in line up to a limit, a region of a virtual context address associated with the cacheable XRI indicators, a protocol associated with the cacheable XRI, a size of a transaction, or work queue information.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: An API in an NPIV-compatible SAN is disclosed that includes functions for creating a vlink, replicating driver software for managing the vlink, monitoring resources in an HBA, or removing a target so that resources can be freed up for other vlinks. The API is part of a driver that communicates with a host OS and also communicates with an HBA to establish the vlinks between the host OS and FC devices. To create vlinks, an “add” function in the API is called by the OS. In addition, when a new vlink is created, a single version of an HBA interface function block is maintained in the driver, but a discovery function block, SCSI bus function block, and I/O function block are all duplicated, forming one logical vlink driver for each vlink. To obtain HBA resource information, a resource monitoring functions in the API may be called by the OS.