Patents by Inventor James Xuan Dinh

James Xuan Dinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8782289
    Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: July 15, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David L. Matthews, Hubert E. Brinkmann, James Xuan Dinh, Dwight D. Riley, Paul V. Brownell
  • Patent number: 8174977
    Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: May 8, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul V. Brownell, David L. Matthews, James Xuan Dinh, Hubert E. Brinkmann, Dwight D. Riley, Hahn Vo Norden, Kenneth T. Chin
  • Publication number: 20110082949
    Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.
    Type: Application
    Filed: June 10, 2008
    Publication date: April 7, 2011
    Inventors: David L. Matthews, Hubert E. Brinkmann, James Xuan Dinh, Dwight D. Riley, Paul V. Brownell
  • Publication number: 20090037617
    Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 5, 2009
    Inventors: Dwight D. RILEY, James Xuan Dinh, Barry S. Basile, Kenneth A. Jansen, Hubert E. Brinkmann, David L. Matthews, Paul V. Brownell
  • Publication number: 20090010159
    Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.
    Type: Application
    Filed: July 6, 2007
    Publication date: January 8, 2009
    Inventors: Paul V. Brownell, David L. Matthews, James Xuan Dinh, Hubert E. Brinkmann, Dwight D. Riley, Hahn Vo Norden, Kenneth T. Chin