Patents by Inventor James Yamaguchi

James Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200006367
    Abstract: A 3-D memory module comprising a plurality of packaged integrated memory circuits or devices is mounted to a substrate with integrated pins that are edge-connected on two surfaces where the top surface provides an edge connection from the integrated memory circuits to an orthogonally-mounted memory controller circuit through a wide-word interface. Each integrated memory device can be accessed independently wherein the memory controller is configured to reduce the wide-word interface to a serial interface which is brought to the opposite surface of the memory module for electrical coupling to an external system or printed circuit assembly.
    Type: Application
    Filed: May 9, 2019
    Publication date: January 2, 2020
    Applicant: Irvine Sensors Corporation
    Inventors: Christian Krutzik, James Yamaguchi, Samba He
  • Patent number: 9741680
    Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: August 22, 2017
    Assignee: PFG IP LLC
    Inventors: Randy Bindrup, W. Eric Boyd, John Leon, James Yamaguchi, Angel Pepe
  • Patent number: 9431275
    Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: August 30, 2016
    Assignee: PFG IP LLC
    Inventors: Randy Bindrup, W. Eric Boyd, John Leon, James Yamaguchi, Angel Pepe
  • Patent number: 8637985
    Abstract: A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 28, 2014
    Assignee: ISC8 Inc.
    Inventors: Randy Bindrup, James Yamaguchi, W. Eric Boyd
  • Patent number: 8637140
    Abstract: A method for defining an electrically conductive metalized structure, which may comprise an electrode or trace, on the surface of a three-dimensional element. The three-dimensional element may comprise a glass microsphere or shell resonator. A laser direct write grayscale photolithographic process is used in conjunction with electrically conductive metal deposition processes to define one or more electrically conductive metal structures on the surfaces of the three dimensional element.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: January 28, 2014
    Assignee: ISCS Inc.
    Inventors: James Yamaguchi, W. Eric Boyd
  • Patent number: 8609473
    Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: December 17, 2013
    Assignee: ISC8 Inc.
    Inventors: Peter Lieu, James Yamaguchi, Randy Bindrup, W. Eric Boyd
  • Publication number: 20120211886
    Abstract: A method for fabricating an integrated circuit chip-scale package and a device made from the method. One or more IC chips are mounted on a carrier and a stud bump defined on an IC pad. The stud-bumped IC is encapsulated to define a potted assembly layer which is thinned to expose the stud bump. Conductive first traces are defined and coupled to the stud bump to reroute the IC pads. A dielectric layer is provided and vias defined there through to expose the first traces. Electrically conductive second traces are disposed on the dielectric layer surface that are coupled to the first traces to reroute the IC pads to define a chip scale package.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 23, 2012
    Applicant: ISC8 Inc.
    Inventors: Peter Lieu, James Yamaguchi, Randy Bindrup, W. Eric Boyd
  • Publication number: 20120205801
    Abstract: A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 16, 2012
    Inventors: Randy Bindrup, James Yamaguchi, W. Eric Boyd
  • Publication number: 20120094092
    Abstract: A method for defining an electrically conductive metalized structure, which may comprise an electrode or trace, on the surface of a three-dimensional element. The three-dimensional element may comprise a glass microsphere or shell resonator. A laser direct write grayscale photolithographic process is used in conjunction with electrically conductive metal deposition processes to define one or more electrically conductive metal structures on the surfaces of the three dimensional element.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 19, 2012
    Applicant: Irvine Sensors Corporation
    Inventors: James Yamaguchi, W. Eric Boyd
  • Publication number: 20120069528
    Abstract: A process and product made from the process is disclosed to minimize solder collapse during solder reflow. Predetermined bond pads on a layer or component have a solder paste such as Sn63 solder paste with a first lower reflow temperature applied and a spacer element such as an SAC solder ball or stud bump having a predetermined geometry with a second higher reflow temperature applied. The SAC solder balls or stud bumps act as spacing elements but do not interact with the solder paste such that the solder paste may be reflowed while precisely maintaining the space between the layers.
    Type: Application
    Filed: August 15, 2011
    Publication date: March 22, 2012
    Applicant: Irvine Sensors Corporation
    Inventors: Randy Bindrup, James Yamaguchi, W. Eric Boyd
  • Publication number: 20120068333
    Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
    Type: Application
    Filed: August 15, 2011
    Publication date: March 22, 2012
    Applicant: Irvine Sensors Corporation
    Inventors: Randy Bindrup, W. Eric Boyd, John Leon, James Yamaguchi
  • Publication number: 20120068336
    Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.
    Type: Application
    Filed: October 12, 2011
    Publication date: March 22, 2012
    Applicant: Irvine Sensors Corporation
    Inventors: Peter Lieu, James Yamaguchi, Randy Bindrup, W. Eric Boyd
  • Publication number: 20110227603
    Abstract: A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 22, 2011
    Applicant: Irvine Sensors Corporation
    Inventors: John Leon, James Yamaguchi, W. Eric Boyd, Volkan Ozguz
  • Publication number: 20110031982
    Abstract: A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 10, 2011
    Applicant: Irvine Sensors Corporation
    Inventors: John Leon, James Yamaguchi, Volkan Ozguz, W. Eric Boyd
  • Publication number: 20100291735
    Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Inventors: Volkan Ozguz, Angel Pepe, James Yamaguchi, W. Eric Boyd, Douglas Albert, Andrew Camien
  • Patent number: 7786562
    Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: August 31, 2010
    Inventors: Volkan Ozguz, Angel Pepe, James Yamaguchi, W. Eric Boyd, Douglas Albert, Andrew Camien
  • Patent number: 7335576
    Abstract: A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: February 26, 2008
    Assignee: Irvine Sensors Corp.
    Inventors: Ludwig David, James Yamaguchi, Stuart Clark, W. Eric Boyd
  • Patent number: 7239012
    Abstract: A pre-formed integrated circuit chip-containing module formed from layers is disclosed. Each layer contains an integrated circuit chip that is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: July 3, 2007
    Assignee: Irvine Sensors Corp.
    Inventors: Angel Pepe, James Yamaguchi
  • Publication number: 20060079072
    Abstract: A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate remove to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.
    Type: Application
    Filed: August 5, 2005
    Publication date: April 13, 2006
    Inventors: Ludwig David, James Yamaguchi, Stewart Clark, W. Boyd
  • Patent number: RE43877
    Abstract: A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: December 25, 2012
    Assignee: Aprolase Development Co., LLC
    Inventors: David Ludwig, James Yamaguchi, Stewart Clark, W. Eric Boyd