Patents by Inventor James Yarbrough

James Yarbrough has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11340794
    Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 24, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mark Himelstein, James Yarbrough, Rick Carlson, Vishwas Durai, Vikram Venkataraghavan, Bruce A. Wilford, Grace Ho, Bill Katz, Richard Van Gaasbeck, Dan Arai, David R. Emberson
  • Patent number: 11010054
    Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 18, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mark Himelstein, Bruce Wilford, Richard Van Gaasbeck, Todd Wilde, Rick Carlson, Vikram Venkataraghavan, Vishwas Durai, James Yarbrough, Blair Barnett
  • Patent number: 10289491
    Abstract: In general, embodiments of the technology relate to a method for storing data. More specifically, the method may include selecting a first RAID grid location in a RAID grid, where the first RAID grid location is flagged, selecting a second RAID grid location in the RAID grid, making a first determination that the second RAID grid location is not flagged, in response to the first determination, loading first data associated with the second RAID grid location into a cache, calculating a parity value for a corresponding set of RAID grid locations in a data grid using the first data in the cache, where the first RAID grid location and the second RAID grid location are in the set of RAID grid locations, and storing at least a copy of the first data and the parity value in a storage array comprising persistent storage.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 14, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Grace Ho, James Yarbrough
  • Publication number: 20190121553
    Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Mark Himelstein, James Yarbrough, Rick Carlson, Vishwas Durai, Vikram Venkataraghavan, Bruce A. Wilford, Grace Ho, Bill Katz, Rich Van Gaasbeck, Daniel Arai, David R. Emberson
  • Patent number: 10209904
    Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: February 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Mark Himelstein, James Yarbrough, Rick Carlson, Vishwas Durai, Vikram Venkataraghavan, Bruce A. Wilford, Grace Ho, Bill Katz, Rich Van Gaasbeck, Daniel Arai, David R. Emberson
  • Patent number: 10004968
    Abstract: A helmet training aid for obscuring the vision of a user. The helmet training aid includes a panel having a pair of distal ends securely affixed to a pair of opposing blinders. A fastener is secured at a lower end of each blinder, wherein the fastener removably secures each blinder to an opposing side of a helmet such that an upper end of each blinder covers an open portion of the helmet therebetween a brim and a cage of the helmet. The panel contains one or more fasteners on a first surface that removably secures to the cage of the helmet. In an alternative embodiment, opposing sidewalls of the blinders flare outwardly from the lower end to the upper end, the fastener on each blinder is secured to a protrusion at the lower end, and the panel is made of a mesh material.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: June 26, 2018
    Inventors: Steven Valadez, James Yarbrough
  • Publication number: 20180036617
    Abstract: A helmet training aid for obscuring the vision of a user. The helmet training aid includes a panel having a pair of distal ends securely affixed to a pair of opposing blinders. A fastener is secured at a lower end of each blinder, wherein the fastener removably secures each blinder to an opposing side of a helmet such that an upper end of each blinder covers an open portion of the helmet therebetween a brim and a cage of the helmet. The panel contains one or more fasteners on a first surface that removably secures to the cage of the helmet. In an alternative embodiment, opposing sidewalls of the blinders flare outwardly from the lower end to the upper end, the fastener on each blinder is secured to a protrusion at the lower end, and the panel is made of a mesh material.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 8, 2018
    Inventors: Steven Valadez, James Yarbrough
  • Patent number: 9582302
    Abstract: A computing system is configured to use a trampoline to isolate sensitive code in a virtual environment and in other applications. An import table may describe the entry points of a privileged code module or driver that generates privileged code. A system and method loads a shadow kernel to facilitate isolating the linkage between drivers and the rest of the system. The shadow kernel may be a copy of the operating system kernel that does not have the same integral position in the operation of the computing device. The shadow kernel may be used as a template for creating a jump table to redirect more critical privileged resource access requests from specially loaded kernel mode drivers to the PVM. All requests may pass through the PVM, which redirects non-critical functions to the original kernel. Multiple copies of a given driver or code module may be loaded in a given session.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 28, 2017
    Assignee: Citrix Systems, Inc.
    Inventors: Michael Larkin, James Yarbrough, Yashabh Sethi
  • Patent number: 8407699
    Abstract: A computing system is configured to use a trampoline to isolate sensitive code in a virtual environment and in other applications. An import table may describe the entry points of a privileged code module or driver that generates privileged code. A system and method loads a shadow kernel to facilitate isolating the linkage between drivers and the rest of the system. The shadow kernel may be a copy of the operating system kernel that does not have the same integral position in the operation of the computing device. The shadow kernel may be used as a template for creating a jump table to redirect more critical privileged resource access requests from specially loaded kernel mode drivers to the PVM. All requests may pass through the PVM, which redirects non-critical functions to the original kernel. Multiple copies of a given driver or code module may be loaded in a given session.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: March 26, 2013
    Assignee: Citrix Systems, Inc.
    Inventors: Michael Larkin, James Yarbrough, Yashabh Sethi
  • Publication number: 20090293057
    Abstract: A computing system is configured to use a trampoline to isolate sensitive code in a virtual environment and in other applications. An import table may describe the entry points of a privileged code module or driver that generates privileged code. A system and method loads a shadow kernel to facilitate isolating the linkage between drivers and the rest of the system. The shadow kernel may be a copy of the operating system kernel that does not have the same integral position in the operation of the computing device. The shadow kernel may be used as a template for creating a jump table to redirect more critical privileged resource access requests from specially loaded kernel mode drivers to the PVM. All requests may pass through the PVM, which redirects non-critical functions to the original kernel. Multiple copies of a given driver or code module may be loaded in a given session.
    Type: Application
    Filed: March 5, 2009
    Publication date: November 26, 2009
    Inventors: Michael Larkin, James Yarbrough, Yashabh Sethi