Patents by Inventor James Yik

James Yik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7760719
    Abstract: A packet switching node in a pipelined architecture processing packets received via an input port associated with the packet switching node performs a method, which includes: determining a packet frame type; selectively extracting packet header field values specific to a packet frame type, including packet addressing information; ascribing to the packet a preliminary action to be performed; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into a packet flow; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: July 20, 2010
    Assignee: Conexant Systems, Inc.
    Inventors: James Yik, Rong-Feng Chang, Eric Lin, John Ta, Craig Barrack
  • Patent number: 7142551
    Abstract: Methods and apparatus are presented for scheduling playback for voice data sample packet payloads conveyed over best-effort packet-switched infrastructure. The hardware implementation presented provides support for concurrent and independent comfort noise insertion and for dynamic clock adjustment for telephone sessions provisioned concurrently without making recourse to signaling. The apparatus and methods support high density solutions scaleing up to large numbers of concurrently provisioned telephone sessions.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: November 28, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: Craig Barrack, James Yik
  • Patent number: 7085704
    Abstract: Methods and apparatus for hardware scheduling processes handling are presented. The apparatus includes a table of task lists. Each task list has specifications of processes requiring handling during a corresponding time interval. Each task list is parsed by a scheduler during a corresponding interval and the processes specified therein are handled. The methods of process handling may include a determination of a next time interval in which the process requires handling and inserting of process specifications in task lists corresponding to the determined next handling times. Implementations are also presented in which task lists specify work units requiring handling during corresponding time intervals. The entire processing power of the scheduler is used to schedule processes for handling. Advantages are derived from an efficient use of the processing power of the scheduler as the number of processes is increased.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: August 1, 2006
    Assignee: Zarlink Semicorporation V.N. Inc.
    Inventors: James Yik, Craig Barrack
  • Publication number: 20060002386
    Abstract: A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Applicant: Zarlink Semiconductor Inc.
    Inventors: James Yik, Rong-Feng Chang, Eric Lin, John Ta, Craig Barrack
  • Publication number: 20040170163
    Abstract: Data structures for efficient tracking Real-Time Control Protocol (RTCP) statistical information reported in connection with a Real-Time Protocol (RTP) encapsulated data stream, and a signaling protocol for updating corresponding statistical information between a hardware statistics information collection function and a software statistics information processing function is presented. Hardware data structure and software data structure specifications take into account: the arrival rate of RTCP statistics reports, the rate of generation of RTP packets, expected communication session duration, statistics information processing bandwidth, etc.; to provide a balance between hardware statistics information tracking, timely update of statistics information processed by software, while reducing statistics information update overheads in support of high density data streaming solutions.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Applicant: ZARLINK SEMICONDUCTOR V.N. INC.
    Inventors: James Yik, Lijen Ko
  • Publication number: 20040117468
    Abstract: A multi-fields (MF) classifier that categorizes each packet into a “QoS index,” instead of a priority queue number directly. The invention comprises two steps. The first step is to regroup the classified index based on its source port setting. The regrouping may combine two indexes into one, move around the classified category, or filer out traffic for access control purposes. The second step maps the index into different settings for all controllable resources. Some of the controllable resources include, but are not limited to, transmit priority on each egress port, dropping preference on each egress port, egress rate control preference, ingress rate control preference, and buffer resource class.
    Type: Application
    Filed: December 12, 2002
    Publication date: June 17, 2004
    Inventors: Linghsaio Wang, James Yik
  • Patent number: 6697873
    Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: February 24, 2004
    Assignee: Zarlink Semiconductor V.N., Inc.
    Inventors: James Yik, Linghsiao Wang
  • Publication number: 20040008715
    Abstract: Methods and apparatus are presented for scheduling playback for voice data sample packet payloads conveyed over best-effort packet-switched infrastructure. The hardware implementation presented provides support for concurrent and independent comfort noise insertion and for dynamic clock adjustment for telephone sessions provisioned concurrently without making recourse to signaling. The apparatus and methods support high density solutions scaleing up to large numbers of concurrently provisioned telephone sessions.
    Type: Application
    Filed: July 15, 2002
    Publication date: January 15, 2004
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Craig Barrack, James Yik
  • Publication number: 20040001494
    Abstract: Architecture for generating a playback time from a AAL2 SSCS voice packet sequence number in a stream-based application. The architecture comprises an event scheduler engine for initiating control parameters for an interpretive window associated with a packet stream; a sliding window engine for controlling the interpretive window according to the control parameters; and an arrival engine that maps the packet sequence number to an expected playback time in accordance with an association created between the packet sequence number and the expected playback time by the interpretive window.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 1, 2004
    Applicant: Zarlink Semiconductor V.N. Inc
    Inventors: Craig I. Barrack, James Yik
  • Publication number: 20040003020
    Abstract: Methods and apparatus for hardware scheduling processes handling are presented. The apparatus includes a table of task lists. Each task list has specifications of processes requiring handling during a corresponding time interval. Each task list is parsed by a scheduler during a corresponding interval and the processes specified therein are handled. The methods of process handling may include a determination of a next time interval in which the process requires handling and inserting of process specifications in task lists corresponding to the determined next handling times. Implementations are also presented in which task lists specify work units requiring handling during corresponding time intervals. The entire processing power of the scheduler is used to schedule processes for handling. Advantages are derived from an efficient use of the processing power of the scheduler as the number of processes is increased.
    Type: Application
    Filed: May 7, 2002
    Publication date: January 1, 2004
    Inventors: James Yik, Craig Barrack
  • Publication number: 20030219007
    Abstract: A packet based real-time data receiver comprising a protocol specific plug-in and a generic playback engine. The protocol specific plug-in receives a packet, parses the packet, generates a timestamp, and forwards the packet to the generic playback engine. The playback engine determining the playback time based on the timestamp, and for playing back the packet at the appropriate time. Any kind of packet may be processed by merely changing the protocol specific plug-in.
    Type: Application
    Filed: May 23, 2002
    Publication date: November 27, 2003
    Inventors: Craig Barrack, James Yik
  • Publication number: 20030026246
    Abstract: Architecture for processing routing information in a data network. A set of routing information entries is provided in a routing database of a first storage location. A subset of the routing information entries is created in a second storage location, which subset of the routing information entries are in the structure of an IP tree. Packet routing information of an incoming packet is extracted, which packet routing information includes multiple byte parts. The second storage location is accessed to compare the multiple byte parts of the packet routing information sequentially with respective entries of the subset of routing information entries to determine forwarding information. The subset of routing information in the second location is adjusted dynamically in response to the availability of the packet routing information in the subset of routing information entries.
    Type: Application
    Filed: June 5, 2002
    Publication date: February 6, 2003
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: James Huang, Eric Lin, Steven Hsieh, James Yik, Ilya Dorfman, George Cravens