Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Abstract: A waste disposal device for sealing waste and a cassette for dispensing film are disclosed. The waste disposal device comprises first and second rollers, each comprising first and second end portions and a joining portion therebetween. The end portions of the first and second rollers are arranged to receive and seal first and second film portions therebetween as the first and second rollers rotate. The joining portions of the first and second rollers are arranged to define an aperture for receiving waste in a first rotary configuration of the rollers and to seal the first and second film portions therebetween in a second rotary configuration of the first and second rollers. The cassette comprises first and second portions comprising respective first and second film dispensers. The first portion is mechanically connected to the second portion. The cassette is moveable between a first, compact configuration and a second, extended configuration.

Abstract: A waste disposal device for sealing waste and a cassette for dispensing film are disclosed. The waste disposal device comprises first and second rollers, each comprising first and second end portions and a joining portion therebetween. The end portions of the first and second rollers are arranged to receive and seal first and second film portions therebetween as the first and second rollers rotate. The joining portions of the first and second rollers are arranged to define an aperture for receiving waste in a first rotary configuration of the rollers and to seal the first and second film portions therebetween in a second rotary configuration of the first and second rollers. The cassette comprises first and second portions comprising respective first and second film dispensers. The first portion is mechanically connected to the second portion. The cassette is moveable between a first, compact configuration and a second, extended configuration.

Abstract: According to the invention, a method for creating an electronic greeting card enclosing an electronic gift is disclosed. In one step, the electronic greeting card selection is received from a sender along with a selection of at least one of a type of electronic gift, an amount for the electronic gift, and an identifier for a receiver of the electronic gift. Payment for the electronic gift is received from a money handler chosen by the sender. A code indicative of the electronic gift is received, whereby the code facilitates redemption of the electronic gift. The code is embedded in the electronic greeting card.

Abstract: Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.

Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.