Abstract: Modeling and testing are used to characterize consequences of a first lithium-ion cell having an internal short. The vulnerability of a second lithium-ion cell being induced into thermal runaway by the energy released by the first cell undergoing an internal short is quantified. Characteristics of the packaging of Li-ion cells within a battery pack are analyzed. Combined, these analyses determine the robustness required of a cell in order to withstand a nearby cell's internal short given that the battery is maintained within the specified operational envelope by a BMS and this envelope is modified in real-time as required to meet the safety requirement. Robustness factors are: age, history of charging/discharging, as well as immediate state of charge and environment. In operation, the cell's operational history is incorporated into a model. When the model indicates cell robustness at a predetermined lower limit, operation of the cell is ceased or limited.

Abstract: A fault tolerant battery management system includes redundancy, with applications including electric vehicles. Portions of its circuitry are constituted in distinct fault domains with control, monitoring, and balancing of cells circuitry fault-effect-isolated from the circuitry associated with built-in real-time testing. Built-in tests are orchestrated in fault domains isolated from the functional circuitry being verified. These built-in tests provide test stimulus unique for each cell measurement. Cell balancing is performed in a fault tolerant manner. It takes at least two independent faults, in two mutually distinct fault domains, to negatively affect balancing capability or to interfere with a redundant circuit's ability to operate. The built-in tests allow operation without the requirement for data cross-compare between redundant measuring electronic elements. Testing and balancing functions are interlocked through encoded enabling methodologies and transmit enables on serial buses.

Abstract: A fault tolerant battery management system includes redundancy, with applications including electric vehicles. Portions of its circuitry are constituted in distinct fault domains with control, monitoring, and balancing of cells circuitry fault-effect-isolated from the circuitry associated with built-in real-time testing. Built-in tests are orchestrated in fault domains isolated from the functional circuitry being verified. These built-in tests provide test stimulus unique for each cell measurement. Cell balancing is performed in a fault tolerant manner. It takes at least two independent faults, in two mutually distinct fault domains, to negatively affect balancing capability or to interfere with a redundant circuit's ability to operate. The built-in tests allow operation without the requirement for data cross-compare between redundant measuring electronic elements. Testing and balancing functions are interlocked through encoded enabling methodologies and transmit enables on serial buses.

Abstract: A can for holding and compacting smokeless tobacco has a bottom member and a lid. The bottom member has a closed bottom, an open top, and a first compacting vane located within the bottom member. The lid is adapted to slidably fit on the bottom member and has a second compacting vane located within the lid. The first compacting vane extends partially across the bottom member, and the second compacting vane extends partially across the lid. The vanes are positioned to contact each other when the can is closed and either the lid or the bottom member is rotated. The lid and/or bottom member are adapted to receive graphics. With smokeless tobacco in the closed can, tobacco located between the first and second vanes in the can is compacted into a tight wad by simply rotating the lid, either clockwise or counter-clockwise, relative to the bottom member.

Abstract: A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at least 10 years, with the threshold voltages defining a window wherein a read voltage for selected memory transistors can be held flat and not intersect the threshold voltages. The lower threshold is selected to be at a zero charge state for one of the two logic levels of the memory.

Abstract: A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at least 10 years, with the threshold voltages defining a window wherein a read voltage for selected memory transistors can be held flat and not intersect the threshold voltages. The lower threshold is selected to be at a zero charge state for one of the two logic levels of the memory.