Abstract: An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor information controlling the generation of its outline and its color pattern. When accessed, this cursor control data is accessed from the non-displayed segment of the memory during each horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Location of the cursor within the video display is determined by a group of position registers which are loaded by the CPU with cursor position data during the vertical blank time. The position registers in conjunction with a group of counters coordinate the insertion of the cursor data into a byte stream of display data as it makes its way to the CRT screen. This display data is stored in the frame buffer and is transferred to the pixel output buffer.

Abstract: An interface controller, situated between a graphics controller and a memory array in a color video display system operable in a read-modify-write mode, configured to detect a select transparency color in whole or in part and to respond by selectively changing the color binary data for the corresponding pixel in a frame buffer. In another aspect, the invention includes drawing modes impelmented by logically combining pixel color binary data in accordance with a defined truth table so as to allow the pixel color data representing a new image to interact in a defined manner based upon color with the data in a previously defined image. As implemented, the binary data in the frame buffer is acted upon in a read-modify-write sequence whereby the various logic operations analyze the source (foreground) pixel data, the destination (background) pixel data, in the context of control signals, to define the pixel color data written into the frame buffer as the color representation for that pixel position.