Abstract: Aspects of the present disclosure provide a processor having: an execution unit configured to execute machine code instructions, at least one of the machine code instructions requiring multiple cycles for its execution; instruction memory holding instructions for execution, wherein the execution unit is configured to access the memory to fetch instructions for execution; an instruction injection mechanism configured to inject an instruction into the execution pipeline during execution of the at least one machine code instruction fetched from the memory; the execution unit configured to pause execution of the at least one machine code instruction, to execute the injected instruction to termination, to detect termination of the injected instruction and to automatically recommence execution of the at least one machine code instruction on detection of termination of the injected instruction.

Abstract: A processor includes: a memory; an execution pipeline having a plurality of pipeline stages for executing an operation on data provided to the execution pipeline and storing a result of the operation into the memory; a receive pipeline having a plurality of pipeline stages for handling incoming data to the processor and storing the incoming data into memory; context status storage for holding an exception indicator of an exception encountered by the receive pipeline whilst it is handling incoming data; the receive pipeline being configured to determine that an exception has been encountered in one of its pipeline stages and to delay committing the exception indicator to the context status storage until a final one of its pipeline stages and to continue to receive and store incoming data into the memory until the exception indicator has been committed.

Abstract: A processor includes: memory; an execution pipeline having a plurality of pipeline stages configured to process data provided to the execution pipeline and to store a result of the processing into the memory; a receive pipeline having a plurality of pipeline stages configured to handle incoming data to the processor and storing the incoming data into memory; context status storage configured to hold an exception indicator of an exception encountered by the execution pipeline while the execution pipeline processes data; wherein the receive pipeline is configured to determine that an exception has been committed to the context status storage by the execution pipeline, to suppress a write to memory of any incoming data to be handled by the receive pipeline and to commit a corresponding exception indicator to the context status storage at a final one of its pipeline stages.

Abstract: Aspects of the present disclosure provide a processor having: an execution unit configured to execute machine code instructions, at least one of the machine code instructions requiring multiple cycles for its execution; instruction memory holding instructions for execution, wherein the execution unit is configured to access the memory to fetch instructions for execution; an instruction injection mechanism configured to inject an instruction into the execution pipeline during execution of the at least one machine code instruction fetched from the memory; the execution unit configured to pause execution of the at least one machine code instruction, to execute the injected instruction to termination, to detect termination of the injected instruction and to automatically recommence execution of the at least one machine code instruction on detection of termination of the injected instruction.

Abstract: A processor includes: a memory; an execution pipeline having a plurality of pipeline stages for executing an operation on data provided to the execution pipeline and storing a result of the operation into the memory; a receive pipeline having a plurality of pipeline stages for handling incoming data to the processor and storing the incoming data into memory; context status storage for holding an exception indicator of an exception encountered by the receive pipeline whilst it is handling incoming data; the receive pipeline being configured to determine that an exception has been encountered in one of its pipeline stages and to delay committing the exception indicator to the context status storage until a final one of its pipeline stages and to continue to receive and store incoming data into the memory until the exception indicator has been committed.

Abstract: A processor includes: memory; an execution pipeline having a plurality of pipeline stages configured to process data provided to the execution pipeline and to store a result of the processing into the memory; a receive pipeline having a plurality of pipeline stages configured to handle incoming data to the processor and storing the incoming data into memory; context status storage configured to hold an exception indicator of an exception encountered by the execution pipeline while the execution pipeline processes data; wherein the receive pipeline is configured to determine that an exception has been committed to the context status storage by the execution pipeline, to suppress a write to memory of any incoming data to be handled by the receive pipeline and to commit a corresponding exception indicator to the context status storage at a final one of its pipeline stages.