Patents by Inventor Jamie Randall Kuesel
Jamie Randall Kuesel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11671102Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.Type: GrantFiled: December 14, 2021Date of Patent: June 6, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Daniel Vasquez Lopez, Kenneth Reneris, Jason Michael Lee, Michael B. Goulding, Paul W. Accisano, Matus Lipka, Jamie Randall Kuesel, Srinivas Raghu Gatta
-
Publication number: 20220109448Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.Type: ApplicationFiled: December 14, 2021Publication date: April 7, 2022Inventors: Daniel VASQUEZ LOPEZ, Kenneth RENERIS, Jason Michael LEE, Michael B. GOULDING, Paul W. ACCISANO, Matus LIPKA, Jamie Randall KUESEL, Srinivas Raghu GATTA
-
Patent number: 11233515Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes processing information pertaining to connectivity among superconducting components and nodes included in a shared floor plan to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of the shared floor plan. The method further includes generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a target inductance of wires for routing signals among the superconducting components and the nodes included in the shared floor plan. The method further includes scheduling parallel execution of tasks for routing wires among a subset of the superconducting components and the nodes within any of the plurality of inflated areas of reach satisfying a geometric constraint.Type: GrantFiled: May 29, 2020Date of Patent: January 25, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Daniel Vasquez Lopez, Kenneth Reneris, Jason Michael Lee, Michael B. Goulding, Paul W. Accisano, Matus Lipka, Jamie Randall Kuesel, Srinivas Raghu Gatta
-
Publication number: 20210376835Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes processing information pertaining to connectivity among superconducting components and nodes included in a shared floor plan to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of the shared floor plan. The method further includes generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a target inductance of wires for routing signals among the superconducting components and the nodes included in the shared floor plan. The method further includes scheduling parallel execution of tasks for routing wires among a subset of the superconducting components and the nodes within any of the plurality of inflated areas of reach satisfying a geometric constraint.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Daniel VASQUEZ LOPEZ, Kenneth RENERIS, Jason Michael LEE, Michael B. GOULDING, Paul W. ACCISANO, Matus LIPKA, Jamie Randall KUESEL, Srinivas Raghu GATTA
-
Patent number: 7970980Abstract: A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.Type: GrantFiled: December 15, 2004Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Jamie Randall Kuesel
-
Patent number: 7757032Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.Type: GrantFiled: August 20, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Giora Biran, Robert Allen Drehmel, Robert Spencer Horton, Mark E. Kautzman, Jamie Randall Kuesel, Ming-i Mark Lin, Eric Oliver Mejdrich, Clarence Rosser Ogilvie, Charles S. Woodruff
-
Patent number: 7469312Abstract: A method for bridging between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a method for bridging between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI).Type: GrantFiled: February 24, 2005Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: Giora Biran, Robert Allen Drehmel, Robert Spencer Horton, Mark E. Kautzman, Jamie Randall Kuesel, Ming-i Mark Lin, Eric Oliver Mejdrich, Clarence Rosser Ogilvie, Charles S. Woodruff
-
Publication number: 20080307147Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.Type: ApplicationFiled: August 20, 2008Publication date: December 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Robert Allen Drehmel, Robert Spencer Horton, Mark E. Kautzman, Jamie Randall Kuesel, Ming-i Mark Lin, Eric Oliver Mejdrich, Clarence Rosser Ogilvie, Charles S. Woodruff
-
Patent number: 7296108Abstract: An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data transfers transparent to the receiving processor. The alignment mechanism detects an unaligned transfer in the bus command queue and forms multiple commands of aligned data to send to the processor.Type: GrantFiled: May 26, 2005Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Bruce Leroy Beukema, Jamie Randall Kuesel, Robert Allen Shearer, Charles David Wait
-
Patent number: 7234017Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.Type: GrantFiled: February 24, 2005Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Giora Biran, Matthew Adam Cushing, Robert Allen Drehmel, Allen James Gavin, Mark E. Kautzman, Jamie Randall Kuesel, Ming-I Mark Lin, David Arnold Luick, James Anthony Marcella, Mark Owen Maxson, Eric Oliver Mejdrich, Adam James Muff, Clarence Rosser Ogilvie, Charles S. Woodruff