Patents by Inventor Jamieson Wardall

Jamieson Wardall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor component and method of manufacture
    Patent number: 8461670
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component is configured to permit the determination of circuit parameters. A high side FET has a gate terminal coupled to an output terminal of a high side gate drive circuit, a drain terminal coupled for receiving an input voltage, and a source terminal coupled to the drain terminal of a low side FET. The gate terminal of the low side FET is coupled to the output terminal of low side drive circuit and the source terminal of the low side FET is coupled for receiving a source of operating potential. The high side gate drive circuit has a bias terminal coupled for receiving a floating potential where the bias terminal is electrically isolated or decoupled from the commonly connected source and drain terminals of the high side FET and the low side FET, respectively.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Phillip Celaya, Yeu Wen Lee, Weng Onn Low, Virgilio Abalos, Jr., Jamieson Wardall
  • SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
    Publication number: 20110298115
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component is configured to permit the determination of circuit parameters. A high side FET has a gate terminal coupled to an output terminal of a high side gate drive circuit, a drain terminal coupled for receiving an input voltage, and a source terminal coupled to the drain terminal of a low side FET. The gate terminal of the low side FET is coupled to the output terminal of low side drive circuit and the source terminal of the low side FET is coupled for receiving a source of operating potential. The high side gate drive circuit has a bias terminal coupled for receiving a floating potential where the bias terminal is electrically isolated or decoupled from the commonly connected source and drain terminals of the high side FET and the low side FET, respectively.
    Type: Application
    Filed: June 30, 2010
    Publication date: December 8, 2011
    Inventors: Phillip Celaya, Yeu Wen Lee, Weng Onn Low, Virgilio Abalos, JR., Jamieson Wardall