Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.

Abstract: A method, system and product for determining error infliction probability or probability. The method comprises obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles; and outputting the SEIP of the node.

Abstract: A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.

Abstract: A method, system and product for determining error infliction probability or probability. The method comprises obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles; and outputting the SEIP of the node.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.