Patents by Inventor Jamil Raja Mazzawi

Jamil Raja Mazzawi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11068629
    Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: July 20, 2021
    Assignee: OPTIMA DESIGN AUTOMATION LTD.
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Publication number: 20200143096
    Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Patent number: 10565337
    Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 18, 2020
    Assignee: OPTIMA DESIGN AUTOMATION LTD
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Patent number: 10502779
    Abstract: A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 10, 2019
    Assignee: OPTIMA DESIGN AUTOMATION LTD.
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Publication number: 20180357350
    Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 13, 2018
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Patent number: 10025895
    Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: July 17, 2018
    Assignee: OPTIMA DESIGN AUTOMATION LTD
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Publication number: 20160370429
    Abstract: A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.
    Type: Application
    Filed: February 17, 2016
    Publication date: December 22, 2016
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Patent number: 9430599
    Abstract: A method, system and product for determining error infliction probability or probability. The method comprises obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles; and outputting the SEIP of the node.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: August 30, 2016
    Assignee: OPTIMA DESIGN AUTOMATION LTD
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Publication number: 20160161557
    Abstract: A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.
    Type: Application
    Filed: February 17, 2016
    Publication date: June 9, 2016
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Publication number: 20150234967
    Abstract: A method, system and product for determining error infliction probability or probability. The method comprises obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles; and outputting the SEIP of the node.
    Type: Application
    Filed: January 21, 2015
    Publication date: August 20, 2015
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Publication number: 20150234962
    Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 20, 2015
    Applicant: OPTIMA DESIGN AUTOMATION LTD
    Inventor: Jamil Raja Mazzawi