Patents by Inventor Jamin F. Fen

Jamin F. Fen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8148221
    Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: April 3, 2012
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Khee Yong Lim, Victor Chan, Eng Hua Lim, Wenhe Lin, Jamin F. Fen
  • Publication number: 20100041242
    Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 18, 2010
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Khee Yong LIM, Victor CHAN, Eng Hua LIM, Wenhe LIN, Jamin F. FEN
  • Patent number: 7615433
    Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 10, 2009
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines (IBM)
    Inventors: Khee Yong Lim, Victor Chan, Eng Hua Lim, Wenhe Lin, Jamin F. Fen
  • Publication number: 20080142897
    Abstract: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG, INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventors: Young Way Teh, Xiangdong Chen, Jamin F. Fen, Jun Jung Kim, Daewon Yang, Roman Knoefler, Michael P. Belyansky